
Kiesha Rose Bryant
Supervisory Patent Examiner (ID: 12435, Phone: (571)272-1844 , Office: P/2800 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2891 |
| Total Applications | 376 |
| Issued Applications | 266 |
| Pending Applications | 8 |
| Abandoned Applications | 102 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6341511
[patent_doc_number] => 20100329745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'PROCESS FOR PRODUCING SURFACE EMITTING LASER, PROCESS FOR PRODUCING SURFACE EMITTING LASER ARRAY, AND OPTICAL APPARATUS INCLUDING SURFACE EMITTING LASER ARRAY PRODUCED BY THE PROCESS'
[patent_app_type] => utility
[patent_app_number] => 12/881399
[patent_app_country] => US
[patent_app_date] => 2010-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6509
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0329/20100329745.pdf
[firstpage_image] =>[orig_patent_app_number] => 12881399
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/881399 | PROCESS FOR PRODUCING SURFACE EMITTING LASER, PROCESS FOR PRODUCING SURFACE EMITTING LASER ARRAY, AND OPTICAL APPARATUS INCLUDING SURFACE EMITTING LASER ARRAY PRODUCED BY THE PROCESS | Sep 13, 2010 | Abandoned |
Array
(
[id] => 5469866
[patent_doc_number] => 20090243032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'ELECTRICAL FUSE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/056289
[patent_app_country] => US
[patent_app_date] => 2008-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3423
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20090243032.pdf
[firstpage_image] =>[orig_patent_app_number] => 12056289
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/056289 | ELECTRICAL FUSE STRUCTURE | Mar 26, 2008 | Abandoned |
Array
(
[id] => 4749025
[patent_doc_number] => 20080157095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Semiconductor Devices Having Single Crystalline Silicon Layers'
[patent_app_type] => utility
[patent_app_number] => 12/045890
[patent_app_country] => US
[patent_app_date] => 2008-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6672
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20080157095.pdf
[firstpage_image] =>[orig_patent_app_number] => 12045890
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/045890 | Semiconductor Devices Having Single Crystalline Silicon Layers | Mar 10, 2008 | Abandoned |
Array
(
[id] => 4805991
[patent_doc_number] => 20080169569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-17
[patent_title] => 'Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 12/003718
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6761
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20080169569.pdf
[firstpage_image] =>[orig_patent_app_number] => 12003718
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/003718 | Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device | Dec 30, 2007 | Abandoned |
Array
(
[id] => 5361104
[patent_doc_number] => 20090035898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'METHOD OF FABRICATING A LAYER WITH TINY STRUCTURE AND THIN FILM TRANSISTOR COMPRISING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/874820
[patent_app_country] => US
[patent_app_date] => 2007-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3141
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20090035898.pdf
[firstpage_image] =>[orig_patent_app_number] => 11874820
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/874820 | METHOD OF FABRICATING A LAYER WITH TINY STRUCTURE AND THIN FILM TRANSISTOR COMPRISING THE SAME | Oct 17, 2007 | Abandoned |
Array
(
[id] => 4930531
[patent_doc_number] => 20080001306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'HIGH DENSITY NANOSTRUCTURED INTERCONNECTION'
[patent_app_type] => utility
[patent_app_number] => 11/852413
[patent_app_country] => US
[patent_app_date] => 2007-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2927
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20080001306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11852413
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/852413 | High density nanostructured interconnection | Sep 9, 2007 | Issued |
Array
(
[id] => 4731328
[patent_doc_number] => 20080048324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'Fabricating Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/844478
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1270
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20080048324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11844478
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844478 | Fabricating Semiconductor Device | Aug 23, 2007 | Abandoned |
Array
(
[id] => 4733873
[patent_doc_number] => 20080050852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'MANUFACTURING OF FLEXIBLE DISPLAY DEVICE PANEL'
[patent_app_type] => utility
[patent_app_number] => 11/839358
[patent_app_country] => US
[patent_app_date] => 2007-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5352
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20080050852.pdf
[firstpage_image] =>[orig_patent_app_number] => 11839358
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/839358 | MANUFACTURING OF FLEXIBLE DISPLAY DEVICE PANEL | Aug 14, 2007 | Abandoned |
Array
(
[id] => 4669929
[patent_doc_number] => 20080044989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'PHOTOMASK AND ITS METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 11/832270
[patent_app_country] => US
[patent_app_date] => 2007-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3903
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20080044989.pdf
[firstpage_image] =>[orig_patent_app_number] => 11832270
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/832270 | Photomask and its method of manufacture | Jul 31, 2007 | Issued |
Array
(
[id] => 592627
[patent_doc_number] => 07436015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-14
[patent_title] => 'Driver for driving a load using a charge pump circuit'
[patent_app_type] => utility
[patent_app_number] => 11/695533
[patent_app_country] => US
[patent_app_date] => 2007-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 4268
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/436/07436015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11695533
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/695533 | Driver for driving a load using a charge pump circuit | Apr 1, 2007 | Issued |
Array
(
[id] => 4719053
[patent_doc_number] => 20080241575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'SELECTIVE ALUMINUM DOPING OF COPPER INTERCONNECTS AND STRUCTURES FORMED THEREBY'
[patent_app_type] => utility
[patent_app_number] => 11/692330
[patent_app_country] => US
[patent_app_date] => 2007-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2538
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20080241575.pdf
[firstpage_image] =>[orig_patent_app_number] => 11692330
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692330 | SELECTIVE ALUMINUM DOPING OF COPPER INTERCONNECTS AND STRUCTURES FORMED THEREBY | Mar 27, 2007 | Abandoned |
Array
(
[id] => 795882
[patent_doc_number] => 07429798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Integrated circuit package-in-package system'
[patent_app_type] => utility
[patent_app_number] => 11/690703
[patent_app_country] => US
[patent_app_date] => 2007-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3805
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/429/07429798.pdf
[firstpage_image] =>[orig_patent_app_number] => 11690703
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/690703 | Integrated circuit package-in-package system | Mar 22, 2007 | Issued |
Array
(
[id] => 5253381
[patent_doc_number] => 20070134837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Surface shape recognition sensor and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/704024
[patent_app_country] => US
[patent_app_date] => 2007-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_no_of_words] => 9755
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[pdf_file] => publications/A1/0134/20070134837.pdf
[firstpage_image] =>[orig_patent_app_number] => 11704024
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704024 | Method of fabricating a surface shape recognition sensor | Feb 6, 2007 | Issued |
Array
(
[id] => 5214903
[patent_doc_number] => 20070103983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Nonvolatile Semiconductor Memory'
[patent_app_type] => utility
[patent_app_number] => 11/617425
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 181
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[patent_no_of_words] => 45101
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20070103983.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617425
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617425 | Nonvolatile semiconductor memory | Dec 27, 2006 | Issued |
Array
(
[id] => 888065
[patent_doc_number] => 07348271
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls'
[patent_app_type] => utility
[patent_app_number] => 11/644184
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/07/348/07348271.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644184 | Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls | Dec 21, 2006 | Issued |
Array
(
[id] => 4879882
[patent_doc_number] => 20080153265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer'
[patent_app_type] => utility
[patent_app_number] => 11/614369
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20080153265.pdf
[firstpage_image] =>[orig_patent_app_number] => 11614369
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614369 | Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer | Dec 20, 2006 | Abandoned |
Array
(
[id] => 5120100
[patent_doc_number] => 20070141814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'PROCESS FOR PRODUCING A FREE-STANDING III-N LAYER, AND FREE-STANDING III-N SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/613609
[patent_app_country] => US
[patent_app_date] => 2006-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0141/20070141814.pdf
[firstpage_image] =>[orig_patent_app_number] => 11613609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/613609 | PROCESS FOR PRODUCING A FREE-STANDING III-N LAYER, AND FREE-STANDING III-N SUBSTRATE | Dec 19, 2006 | Abandoned |
Array
(
[id] => 4866899
[patent_doc_number] => 20080145958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS'
[patent_app_type] => utility
[patent_app_number] => 11/611258
[patent_app_country] => US
[patent_app_date] => 2006-12-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0145/20080145958.pdf
[firstpage_image] =>[orig_patent_app_number] => 11611258
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611258 | MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS | Dec 14, 2006 | Abandoned |
Array
(
[id] => 390613
[patent_doc_number] => 07301209
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-27
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/634904
[patent_app_country] => US
[patent_app_date] => 2006-12-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/301/07301209.pdf
[firstpage_image] =>[orig_patent_app_number] => 11634904
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/634904 | Semiconductor device | Dec 6, 2006 | Issued |
Array
(
[id] => 5031566
[patent_doc_number] => 20070096105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Methods of fabricating a semiconductor device using angled implantation'
[patent_app_type] => utility
[patent_app_number] => 11/604915
[patent_app_country] => US
[patent_app_date] => 2006-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4355
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20070096105.pdf
[firstpage_image] =>[orig_patent_app_number] => 11604915
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/604915 | Methods of fabricating a semiconductor device using angled implantation | Nov 27, 2006 | Issued |