Kiesha Rose Bryant

Array ( [id] => 800592 [patent_doc_number] => 07425739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/197552 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 180 [patent_figures_cnt] => 227 [patent_no_of_words] => 45079 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425739.pdf [firstpage_image] =>[orig_patent_app_number] => 11197552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5765888 [patent_doc_number] => 20050263888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Integrated circuit assemblies and assembly methods' [patent_app_type] => utility [patent_app_number] => 11/196049 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7324 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263888.pdf [firstpage_image] =>[orig_patent_app_number] => 11196049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7045717 [patent_doc_number] => 20050250312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Structure and process of metal interconnects' [patent_app_type] => utility [patent_app_number] => 11/155729 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4250 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250312.pdf [firstpage_image] =>[orig_patent_app_number] => 11155729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 383397 [patent_doc_number] => 07307349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface' [patent_app_type] => utility [patent_app_number] => 11/150129 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 5118 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307349.pdf [firstpage_image] =>[orig_patent_app_number] => 11150129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5828290 [patent_doc_number] => 20060063319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/144697 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063319.pdf [firstpage_image] =>[orig_patent_app_number] => 11144697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 383353 [patent_doc_number] => 07307305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/143197 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 49 [patent_no_of_words] => 11053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307305.pdf [firstpage_image] =>[orig_patent_app_number] => 11143197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5605536 [patent_doc_number] => 20060267052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Split trunk pixel layout' [patent_app_type] => utility [patent_app_number] => 11/126307 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3422 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267052.pdf [firstpage_image] =>[orig_patent_app_number] => 11126307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6942584 [patent_doc_number] => 20050194632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method of making nonvolatile transistor pairs with shared control gate' [patent_app_type] => utility [patent_app_number] => 11/120937 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3089 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20050194632.pdf [firstpage_image] =>[orig_patent_app_number] => 11120937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7176547 [patent_doc_number] => 20050189583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Field effect transistors having multiple stacked channels' [patent_app_type] => utility [patent_app_number] => 11/119786 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 12852 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189583.pdf [firstpage_image] =>[orig_patent_app_number] => 11119786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5834781 [patent_doc_number] => 20060246612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Light emitting devices with active layers that extend into opened pits' [patent_app_type] => utility [patent_app_number] => 11/118987 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10437 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246612.pdf [firstpage_image] =>[orig_patent_app_number] => 11118987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 380313 [patent_doc_number] => 07309889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Constructions comprising perovskite-type dielectric' [patent_app_type] => utility [patent_app_number] => 11/119127 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3449 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309889.pdf [firstpage_image] =>[orig_patent_app_number] => 11119127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 827212 [patent_doc_number] => 07402880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Isolation layer for semiconductor devices and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/110027 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2547 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402880.pdf [firstpage_image] =>[orig_patent_app_number] => 11110027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5751096 [patent_doc_number] => 20060220245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Flip chip package and the fabrication thereof' [patent_app_type] => utility [patent_app_number] => 11/099057 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220245.pdf [firstpage_image] =>[orig_patent_app_number] => 11099057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5750945 [patent_doc_number] => 20060220094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Non-volatile memory transistor with nanotube floating gate' [patent_app_type] => utility [patent_app_number] => 11/096857 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1247 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220094.pdf [firstpage_image] =>[orig_patent_app_number] => 11096857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7050895 [patent_doc_number] => 20050186782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Dual damascene interconnect structure with improved electro migration lifetimes' [patent_app_type] => utility [patent_app_number] => 11/090107 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6182 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186782.pdf [firstpage_image] =>[orig_patent_app_number] => 11090107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 826844 [patent_doc_number] => 07402509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Method of forming self-passivating interconnects and resulting devices' [patent_app_type] => utility [patent_app_number] => 11/081187 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5840 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402509.pdf [firstpage_image] =>[orig_patent_app_number] => 11081187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6966620 [patent_doc_number] => 20050233517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/078477 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9371 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233517.pdf [firstpage_image] =>[orig_patent_app_number] => 11078477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 548707 [patent_doc_number] => 07170171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Support ring for use with a contact pad and semiconductor device components including the same' [patent_app_type] => utility [patent_app_number] => 11/075967 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170171.pdf [firstpage_image] =>[orig_patent_app_number] => 11075967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6943254 [patent_doc_number] => 20050195303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Package of solid-state imaging device' [patent_app_type] => utility [patent_app_number] => 11/072257 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5646 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195303.pdf [firstpage_image] =>[orig_patent_app_number] => 11072257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5593924 [patent_doc_number] => 20060157840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'High temperature interconnects for high temperature transducers' [patent_app_type] => utility [patent_app_number] => 11/039587 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20060157840.pdf [firstpage_image] =>[orig_patent_app_number] => 11039587 [rel_patent_id] =>[rel_patent_doc_number] =>)