
Kiesha Rose Bryant
Supervisory Patent Examiner (ID: 4361, Phone: (571)272-1844 , Office: P/2800 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2891 |
| Total Applications | 376 |
| Issued Applications | 266 |
| Pending Applications | 8 |
| Abandoned Applications | 102 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 779551
[patent_doc_number] => 06995419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-07
[patent_title] => 'Semiconductor constructions having crystalline dielectric layers'
[patent_app_type] => utility
[patent_app_number] => 11/027263
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2024
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/995/06995419.pdf
[firstpage_image] =>[orig_patent_app_number] => 11027263
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027263 | Semiconductor constructions having crystalline dielectric layers | Dec 29, 2004 | Issued |
Array
(
[id] => 7036827
[patent_doc_number] => 20050156261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Optical sensor and display'
[patent_app_type] => utility
[patent_app_number] => 11/019647
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5553
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156261.pdf
[firstpage_image] =>[orig_patent_app_number] => 11019647
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/019647 | Optical sensor and display | Dec 22, 2004 | Abandoned |
Array
(
[id] => 881097
[patent_doc_number] => 07355235
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-08
[patent_title] => 'Semiconductor device and method for high-k gate dielectrics'
[patent_app_type] => utility
[patent_app_number] => 11/020377
[patent_app_country] => US
[patent_app_date] => 2004-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4352
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/355/07355235.pdf
[firstpage_image] =>[orig_patent_app_number] => 11020377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/020377 | Semiconductor device and method for high-k gate dielectrics | Dec 21, 2004 | Issued |
Array
(
[id] => 7104045
[patent_doc_number] => 20050106771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Group III-V compound semiconductor and group III-V compound semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/000207
[patent_app_country] => US
[patent_app_date] => 2004-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 28307
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20050106771.pdf
[firstpage_image] =>[orig_patent_app_number] => 11000207
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/000207 | Group III-V compound semiconductor and group III-V compound semiconductor device using the same | Nov 30, 2004 | Issued |
Array
(
[id] => 383401
[patent_doc_number] => 07307353
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-11
[patent_title] => 'Technique for attaching die to leads'
[patent_app_type] => utility
[patent_app_number] => 10/985094
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4705
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/307/07307353.pdf
[firstpage_image] =>[orig_patent_app_number] => 10985094
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/985094 | Technique for attaching die to leads | Nov 8, 2004 | Issued |
Array
(
[id] => 7008383
[patent_doc_number] => 20050062099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Semiconductor device including multiple field effect transistors, with first fets having oxide spacers and the second fets having oxide nitride oxidation protection'
[patent_app_type] => utility
[patent_app_number] => 10/981537
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
[patent_figures_cnt] => 48
[patent_no_of_words] => 25525
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20050062099.pdf
[firstpage_image] =>[orig_patent_app_number] => 10981537
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/981537 | Semiconductor device including multiple field effect transistors, with first fets having oxide spacers and the second fets having oxide nitride oxidation protection | Nov 4, 2004 | Abandoned |
Array
(
[id] => 803606
[patent_doc_number] => 07423310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Charge-trapping memory cell and charge-trapping memory device'
[patent_app_type] => utility
[patent_app_number] => 10/952707
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 4604
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/423/07423310.pdf
[firstpage_image] =>[orig_patent_app_number] => 10952707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/952707 | Charge-trapping memory cell and charge-trapping memory device | Sep 28, 2004 | Issued |
Array
(
[id] => 548261
[patent_doc_number] => 07170138
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-30
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/935177
[patent_app_country] => US
[patent_app_date] => 2004-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 49
[patent_no_of_words] => 10199
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/170/07170138.pdf
[firstpage_image] =>[orig_patent_app_number] => 10935177
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/935177 | Semiconductor device | Sep 7, 2004 | Issued |
Array
(
[id] => 5898267
[patent_doc_number] => 20060043500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/925057
[patent_app_country] => US
[patent_app_date] => 2004-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5952
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20060043500.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925057
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925057 | Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof | Aug 23, 2004 | Abandoned |
Array
(
[id] => 7204540
[patent_doc_number] => 20050052938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Magnetic memory device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/919337
[patent_app_country] => US
[patent_app_date] => 2004-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 15247
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20050052938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10919337
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/919337 | Magnetic memory device | Aug 16, 2004 | Issued |
Array
(
[id] => 5800677
[patent_doc_number] => 20060035474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Increasing retention time for memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/914827
[patent_app_country] => US
[patent_app_date] => 2004-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6410
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20060035474.pdf
[firstpage_image] =>[orig_patent_app_number] => 10914827
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/914827 | Increasing retention time for memory devices | Aug 9, 2004 | Abandoned |
Array
(
[id] => 5293863
[patent_doc_number] => 20090008789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'Method of manufacturing micro tunnel-junction circuit and micro tunnel-junction circuit'
[patent_app_type] => utility
[patent_app_number] => 10/567250
[patent_app_country] => US
[patent_app_date] => 2004-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6928
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20090008789.pdf
[firstpage_image] =>[orig_patent_app_number] => 10567250
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/567250 | Method of manufacturing micro tunnel-junction circuit and micro tunnel-junction circuit | Aug 2, 2004 | Abandoned |
Array
(
[id] => 7056106
[patent_doc_number] => 20050277281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Compliant interconnect and method of formation'
[patent_app_type] => utility
[patent_app_number] => 10/864957
[patent_app_country] => US
[patent_app_date] => 2004-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2309
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0277/20050277281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10864957
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/864957 | Compliant interconnect and method of formation | Jun 9, 2004 | Abandoned |
Array
(
[id] => 900991
[patent_doc_number] => 07339271
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-04
[patent_title] => 'Metal-metal oxide etch stop/barrier for integrated circuit interconnects'
[patent_app_type] => utility
[patent_app_number] => 10/861657
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 4224
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/339/07339271.pdf
[firstpage_image] =>[orig_patent_app_number] => 10861657
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/861657 | Metal-metal oxide etch stop/barrier for integrated circuit interconnects | Jun 2, 2004 | Issued |
Array
(
[id] => 7291661
[patent_doc_number] => 20040211965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/850117
[patent_app_country] => US
[patent_app_date] => 2004-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9574
[patent_no_of_claims] => 74
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20040211965.pdf
[firstpage_image] =>[orig_patent_app_number] => 10850117
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/850117 | Semiconductor device | May 20, 2004 | Issued |
Array
(
[id] => 7220877
[patent_doc_number] => 20050260776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Structure and method for extraction of parasitic junction capacitance in deep submicron technology'
[patent_app_type] => utility
[patent_app_number] => 10/848887
[patent_app_country] => US
[patent_app_date] => 2004-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3217
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20050260776.pdf
[firstpage_image] =>[orig_patent_app_number] => 10848887
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/848887 | Structure and method for extraction of parasitic junction capacitance in deep submicron technology | May 18, 2004 | Abandoned |
Array
(
[id] => 691964
[patent_doc_number] => 07075131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-11
[patent_title] => 'Phase change memory device'
[patent_app_type] => utility
[patent_app_number] => 10/847277
[patent_app_country] => US
[patent_app_date] => 2004-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3118
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/075/07075131.pdf
[firstpage_image] =>[orig_patent_app_number] => 10847277
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/847277 | Phase change memory device | May 16, 2004 | Issued |
Array
(
[id] => 7036766
[patent_doc_number] => 20050156200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Semiconductor integrated circuit, semiconductor integrated circuit design system, and a method for designing semiconductor integrated circuits '
[patent_app_type] => utility
[patent_app_number] => 10/845247
[patent_app_country] => US
[patent_app_date] => 2004-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7683
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156200.pdf
[firstpage_image] =>[orig_patent_app_number] => 10845247
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/845247 | Semiconductor integrated circuit | May 13, 2004 | Issued |
Array
(
[id] => 7220383
[patent_doc_number] => 20050077575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Organic thin film transistor enhanced in charge carrier mobility by virtue of surface relief structure'
[patent_app_type] => utility
[patent_app_number] => 10/845297
[patent_app_country] => US
[patent_app_date] => 2004-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3177
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077575.pdf
[firstpage_image] =>[orig_patent_app_number] => 10845297
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/845297 | Organic thin film transistor enhanced in charge carrier mobility by virtue of surface relief structure | May 13, 2004 | Issued |
Array
(
[id] => 881095
[patent_doc_number] => 07355233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-08
[patent_title] => 'Apparatus and method for multiple-gate semiconductor device with angled sidewalls'
[patent_app_type] => utility
[patent_app_number] => 10/844197
[patent_app_country] => US
[patent_app_date] => 2004-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3726
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/355/07355233.pdf
[firstpage_image] =>[orig_patent_app_number] => 10844197
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/844197 | Apparatus and method for multiple-gate semiconductor device with angled sidewalls | May 11, 2004 | Issued |