Search

Kiet Tuan Nguyen

Examiner (ID: 8901)

Most Active Art Unit
2881
Art Unit(s)
3621, 2878, 2506, 2881
Total Applications
3817
Issued Applications
3374
Pending Applications
195
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17985749 [patent_doc_number] => 20220351786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/868685 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868685
Mitigating a voltage condition of a memory cell in a memory sub-system Jul 18, 2022 Issued
Array ( [id] => 18122866 [patent_doc_number] => 20230008476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => ERROR DETECTION AND CORRECTION METHOD AND CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/858810 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858810
ERROR DETECTION AND CORRECTION METHOD AND CIRCUIT Jul 5, 2022 Pending
Array ( [id] => 18195591 [patent_doc_number] => 20230049110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => INTEGRATED CIRCUIT INCLUDING TEST CIRCUIT AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/857379 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857379
Integrated circuit including test circuit and method of manufacturing the same Jul 4, 2022 Issued
Array ( [id] => 18221475 [patent_doc_number] => 20230060469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => THREE-DIMENSIONAL (3D) STORAGE DEVICE USING WAFER-TO-WAFER BONDING [patent_app_type] => utility [patent_app_number] => 17/854287 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854287
Three-dimensional (3D) storage device using wafer-to-wafer bonding Jun 29, 2022 Issued
Array ( [id] => 17947898 [patent_doc_number] => 20220334917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/854331 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854331
Semiconductor device with user defined operations and associated methods and systems Jun 29, 2022 Issued
Array ( [id] => 18605940 [patent_doc_number] => 11747399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface [patent_app_type] => utility [patent_app_number] => 17/809583 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5883 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809583
Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface Jun 28, 2022 Issued
Array ( [id] => 18702568 [patent_doc_number] => 11789075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Split-scan sense amplifier flip-flop [patent_app_type] => utility [patent_app_number] => 17/853409 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853409
Split-scan sense amplifier flip-flop Jun 28, 2022 Issued
Array ( [id] => 18846177 [patent_doc_number] => 20230408581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY [patent_app_type] => utility [patent_app_number] => 17/841391 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841391
INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY Jun 14, 2022 Pending
Array ( [id] => 18668486 [patent_doc_number] => 11775386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Data storage device and control method for non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/835206 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835206
Data storage device and control method for non-volatile memory Jun 7, 2022 Issued
Array ( [id] => 18818859 [patent_doc_number] => 20230393199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => USING SCAN CHAINS TO READ OUT DATA FROM INTEGRATED SENSORS DURING SCAN TESTS [patent_app_type] => utility [patent_app_number] => 17/834433 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834433
Using scan chains to read out data from integrated sensors during scan tests Jun 6, 2022 Issued
Array ( [id] => 18676878 [patent_doc_number] => 20230314511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SYSTEMS AND METHODS FOR DATABASE SCAN ACCELERATION [patent_app_type] => utility [patent_app_number] => 17/830854 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830854
Systems and methods for database scan acceleration Jun 1, 2022 Issued
Array ( [id] => 18591397 [patent_doc_number] => 11740288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => Localization of multiple scan chain defects per scan chain [patent_app_type] => utility [patent_app_number] => 17/828780 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828780
Localization of multiple scan chain defects per scan chain May 30, 2022 Issued
Array ( [id] => 18810043 [patent_doc_number] => 20230384378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD [patent_app_type] => utility [patent_app_number] => 17/828260 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828260
SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD May 30, 2022 Pending
Array ( [id] => 17853856 [patent_doc_number] => 20220283898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => ERROR CODE CALCULATION ON SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/751217 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751217
Error code calculation on sensing circuitry May 22, 2022 Issued
Array ( [id] => 18686363 [patent_doc_number] => 11782092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-10 [patent_title] => Scan compression through pin data encoding [patent_app_type] => utility [patent_app_number] => 17/747331 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747331
Scan compression through pin data encoding May 17, 2022 Issued
Array ( [id] => 18303395 [patent_doc_number] => 11625298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Memory block defect detection and management [patent_app_type] => utility [patent_app_number] => 17/746754 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746754
Memory block defect detection and management May 16, 2022 Issued
Array ( [id] => 18447544 [patent_doc_number] => 11683125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Polar coding systems, procedures, and signaling [patent_app_type] => utility [patent_app_number] => 17/746795 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 56 [patent_no_of_words] => 19839 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746795
Polar coding systems, procedures, and signaling May 16, 2022 Issued
Array ( [id] => 17834473 [patent_doc_number] => 20220271777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => ACCELERATED ERASURE CODING SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/744329 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744329
Accelerated erasure coding system and method May 12, 2022 Issued
Array ( [id] => 18447469 [patent_doc_number] => 11683050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Memory controller and method of data bus inversion using an error detection correction code [patent_app_type] => utility [patent_app_number] => 17/744311 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744311
Memory controller and method of data bus inversion using an error detection correction code May 12, 2022 Issued
Array ( [id] => 19313594 [patent_doc_number] => 12039411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Performing error correction optimization for quantum services using quantum simulators [patent_app_type] => utility [patent_app_number] => 17/733058 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733058
Performing error correction optimization for quantum services using quantum simulators Apr 28, 2022 Issued
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