
Kim Kwok Chu
Examiner (ID: 4012)
| Most Active Art Unit | 2506 |
| Art Unit(s) | 2752, 2653, 2627, 2516, 2899, 2651, 2506 |
| Total Applications | 1354 |
| Issued Applications | 1184 |
| Pending Applications | 15 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20146734
[patent_doc_number] => 12381081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-05
[patent_title] => Method of breaking through etch stop layer
[patent_app_type] => utility
[patent_app_number] => 18/402563
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 5850
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402563
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402563 | Method of breaking through etch stop layer | Jan 1, 2024 | Issued |
Array
(
[id] => 19087880
[patent_doc_number] => 20240114681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/537244
[patent_app_country] => US
[patent_app_date] => 2023-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537244
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/537244 | Semiconductor device and method for fabricating the same | Dec 11, 2023 | Issued |
Array
(
[id] => 19055029
[patent_doc_number] => 20240096998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => HYBRID CONDUCTIVE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/516373
[patent_app_country] => US
[patent_app_date] => 2023-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6762
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516373
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/516373 | HYBRID CONDUCTIVE STRUCTURES | Nov 20, 2023 | Pending |
Array
(
[id] => 18927135
[patent_doc_number] => 20240030139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => SELF-ALIGNED BURIED POWER RAIL CAP FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/375026
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11253
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375026
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/375026 | Self-aligned buried power rail cap for semiconductor devices | Sep 28, 2023 | Issued |
Array
(
[id] => 18991150
[patent_doc_number] => 20240063119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => TWO-DIMENSIONAL (2D) METAL STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/447701
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7381
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447701
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447701 | Two-dimensional (2D) metal structure and method of forming the same | Aug 9, 2023 | Issued |
Array
(
[id] => 18812576
[patent_doc_number] => 20230386913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/361770
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7502
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361770
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361770 | Source/drain contact formation methods and devices | Jul 27, 2023 | Issued |
Array
(
[id] => 18729416
[patent_doc_number] => 20230343712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => DIFFERENT VIA CONFIGURATIONS FOR DIFFERENT VIA INTERFACE REQUIREMENTS
[patent_app_type] => utility
[patent_app_number] => 18/345388
[patent_app_country] => US
[patent_app_date] => 2023-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345388
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/345388 | Different via configurations for different via interface requirements | Jun 29, 2023 | Issued |
Array
(
[id] => 18729411
[patent_doc_number] => 20230343707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/343784
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14492
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343784
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/343784 | Semiconductor devices and methods of fabricating the same | Jun 28, 2023 | Issued |
Array
(
[id] => 18712867
[patent_doc_number] => 20230335500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => MEMORY DEVICE INCLUDING STAIRCASE STRUCTURE HAVING CONDUCTIVE PADS
[patent_app_type] => utility
[patent_app_number] => 18/214911
[patent_app_country] => US
[patent_app_date] => 2023-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13950
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214911
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/214911 | Memory device including staircase structure having conductive pads | Jun 26, 2023 | Issued |
Array
(
[id] => 18729415
[patent_doc_number] => 20230343711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => Plasma-Damage-Resistant Interconnect Structure and Methods for Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/342335
[patent_app_country] => US
[patent_app_date] => 2023-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342335
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/342335 | Plasma-damage-resistant interconnect structure and methods for forming the same | Jun 26, 2023 | Issued |
Array
(
[id] => 19741163
[patent_doc_number] => 12218008
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Memory device including self-aligned conductive contacts
[patent_app_type] => utility
[patent_app_number] => 18/200852
[patent_app_country] => US
[patent_app_date] => 2023-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 155
[patent_no_of_words] => 18886
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200852
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/200852 | Memory device including self-aligned conductive contacts | May 22, 2023 | Issued |
Array
(
[id] => 18600227
[patent_doc_number] => 20230275028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-31
[patent_title] => DIELECTRIC ON WIRE STRUCTURE TO INCREASE PROCESSING WINDOW FOR OVERLYING VIA
[patent_app_type] => utility
[patent_app_number] => 18/311308
[patent_app_country] => US
[patent_app_date] => 2023-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11386
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311308
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/311308 | Dielectric on wire structure to increase processing window for overlying via | May 2, 2023 | Issued |
Array
(
[id] => 19943670
[patent_doc_number] => 12315806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Electronic device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/306989
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 2312
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306989
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306989 | Electronic device and manufacturing method thereof | Apr 24, 2023 | Issued |
Array
(
[id] => 19528673
[patent_doc_number] => 20240352575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => PLASMA BASED FILM MODIFICATION FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/306111
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3904
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306111
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306111 | Plasma based film modification for semiconductor devices | Apr 23, 2023 | Issued |
Array
(
[id] => 19524003
[patent_doc_number] => 12125743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Via-first process for connecting a contact and a gate electrode
[patent_app_type] => utility
[patent_app_number] => 18/302156
[patent_app_country] => US
[patent_app_date] => 2023-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 16119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302156
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/302156 | Via-first process for connecting a contact and a gate electrode | Apr 17, 2023 | Issued |
Array
(
[id] => 18500665
[patent_doc_number] => 20230223461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units
[patent_app_type] => utility
[patent_app_number] => 18/122427
[patent_app_country] => US
[patent_app_date] => 2023-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122427
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/122427 | Semiconductor constructions, methods of forming transistor gates, and methods of forming NAND cell units | Mar 15, 2023 | Issued |
Array
(
[id] => 18440064
[patent_doc_number] => 20230187359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/164626
[patent_app_country] => US
[patent_app_date] => 2023-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164626
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/164626 | Memory device | Feb 5, 2023 | Issued |
Array
(
[id] => 20146826
[patent_doc_number] => 12381173
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-05
[patent_title] => Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface
[patent_app_type] => utility
[patent_app_number] => 18/067617
[patent_app_country] => US
[patent_app_date] => 2022-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 8744
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067617
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/067617 | Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface | Dec 15, 2022 | Issued |
Array
(
[id] => 19552854
[patent_doc_number] => 12136566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-05
[patent_title] => Semiconductor device and method of manufacture
[patent_app_type] => utility
[patent_app_number] => 17/969396
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8440
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969396
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/969396 | Semiconductor device and method of manufacture | Oct 18, 2022 | Issued |
Array
(
[id] => 19670856
[patent_doc_number] => 12183626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Metal interconnect structure having cap layer with different thicknesses and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/883647
[patent_app_country] => US
[patent_app_date] => 2022-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3219
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883647
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/883647 | Metal interconnect structure having cap layer with different thicknesses and method for fabricating the same | Aug 8, 2022 | Issued |