Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16789362 [patent_doc_number] => 10991801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor device with improved current flow distribution [patent_app_type] => utility [patent_app_number] => 16/752687 [patent_app_country] => US [patent_app_date] => 2020-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18325 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752687
Semiconductor device with improved current flow distribution Jan 25, 2020 Issued
Array ( [id] => 17544057 [patent_doc_number] => 11309190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/746239 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746239
Semiconductor device and method of manufacture Jan 16, 2020 Issued
Array ( [id] => 16981463 [patent_doc_number] => 20210225700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => BARRIER-LESS PREFILLED VIA FORMATION [patent_app_type] => utility [patent_app_number] => 16/744254 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744254
Barrier-less prefilled via formation Jan 15, 2020 Issued
Array ( [id] => 17196012 [patent_doc_number] => 11164777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Top via with damascene line and via [patent_app_type] => utility [patent_app_number] => 16/743955 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5239 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743955 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743955
Top via with damascene line and via Jan 14, 2020 Issued
Array ( [id] => 16966200 [patent_doc_number] => 20210217699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => HYBRID CONDUCTOR INTEGRATION IN POWER RAIL [patent_app_type] => utility [patent_app_number] => 16/738127 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738127
Hybrid conductor integration in power rail Jan 8, 2020 Issued
Array ( [id] => 17018704 [patent_doc_number] => 11088351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Display panels and display devices [patent_app_type] => utility [patent_app_number] => 16/735614 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4479 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735614
Display panels and display devices Jan 5, 2020 Issued
Array ( [id] => 15840895 [patent_doc_number] => 20200135730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/732194 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732194 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732194
Buried channel semiconductor device and method for manufacturing the same Dec 30, 2019 Issued
Array ( [id] => 16936523 [patent_doc_number] => 20210202412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/730390 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730390 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730390
Semiconductor device package and method of manufacturing the same Dec 29, 2019 Issued
Array ( [id] => 17395879 [patent_doc_number] => 11244903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Tungsten structures and methods of forming the structures [patent_app_type] => utility [patent_app_number] => 16/730505 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7911 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730505
Tungsten structures and methods of forming the structures Dec 29, 2019 Issued
Array ( [id] => 17395919 [patent_doc_number] => 11244943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material [patent_app_type] => utility [patent_app_number] => 16/728983 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 11936 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728983
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material Dec 26, 2019 Issued
Array ( [id] => 15807617 [patent_doc_number] => 20200126951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/717068 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717068 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717068
Wafer level integration including design/co-design, structure process, equipment stress management and thermal management Dec 16, 2019 Issued
Array ( [id] => 17310169 [patent_doc_number] => 11211295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => FinFET doping methods and structures thereof [patent_app_type] => utility [patent_app_number] => 16/717398 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717398
FinFET doping methods and structures thereof Dec 16, 2019 Issued
Array ( [id] => 17107449 [patent_doc_number] => 11127675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Interconnection structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/709934 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709934
Interconnection structure and manufacturing method thereof Dec 10, 2019 Issued
Array ( [id] => 16888972 [patent_doc_number] => 20210175169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/709896 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709896
Semiconductor device and manufacturing method of the same Dec 9, 2019 Issued
Array ( [id] => 16021023 [patent_doc_number] => 20200185355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/707926 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707926
Semiconductor device and manufacturing method thereof Dec 8, 2019 Issued
Array ( [id] => 16324425 [patent_doc_number] => 10784400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Mass transfer method for micro-LEDs with a temperature-controlled adhesive layer [patent_app_type] => utility [patent_app_number] => 16/706713 [patent_app_country] => US [patent_app_date] => 2019-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1955 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706713
Mass transfer method for micro-LEDs with a temperature-controlled adhesive layer Dec 6, 2019 Issued
Array ( [id] => 15808179 [patent_doc_number] => 20200127232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => ORGANIC PHOTOELECTRONIC DEVICE AND IMAGE SENSOR AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/704683 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704683
Organic photoelectronic device and image sensor and electronic device Dec 4, 2019 Issued
Array ( [id] => 17381261 [patent_doc_number] => 11239294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/697559 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10526 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697559
Display device and manufacturing method thereof Nov 26, 2019 Issued
Array ( [id] => 16803459 [patent_doc_number] => 10998415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Metal gate scheme for device and methods of forming [patent_app_type] => utility [patent_app_number] => 16/692053 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692053
Metal gate scheme for device and methods of forming Nov 21, 2019 Issued
Array ( [id] => 15656927 [patent_doc_number] => 20200090994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE [patent_app_type] => utility [patent_app_number] => 16/689223 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689223
Semiconductor device with reduced via resistance Nov 19, 2019 Issued
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