Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10385164 [patent_doc_number] => 20150270172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Novel 3D Integration Method using SOI Substrates and Structures Produced Thereby' [patent_app_type] => utility [patent_app_number] => 14/733619 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5965 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733619
Novel 3D Integration Method using SOI Substrates and Structures Produced Thereby Jun 7, 2015 Abandoned
Array ( [id] => 11891019 [patent_doc_number] => 09761584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Buried channel semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/732661 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 4863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732661 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732661
Buried channel semiconductor device and method for manufacturing the same Jun 4, 2015 Issued
Array ( [id] => 10440432 [patent_doc_number] => 20150325444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/732208 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 18779 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732208 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732208
Method for producing an SGT-including semiconductor device Jun 4, 2015 Issued
Array ( [id] => 11483593 [patent_doc_number] => 09590157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Efficient dual metal contact formation for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/730500 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4142 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730500
Efficient dual metal contact formation for a semiconductor device Jun 3, 2015 Issued
Array ( [id] => 12314970 [patent_doc_number] => 09941376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Metal gate scheme for device and methods of forming [patent_app_type] => utility [patent_app_number] => 14/730444 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730444
Metal gate scheme for device and methods of forming Jun 3, 2015 Issued
Array ( [id] => 11753331 [patent_doc_number] => 09711350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Methods for semiconductor passivation by nitridation' [patent_app_type] => utility [patent_app_number] => 14/729510 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5035 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729510 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729510
Methods for semiconductor passivation by nitridation Jun 2, 2015 Issued
Array ( [id] => 14333021 [patent_doc_number] => 10297539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Electronic device including soldered surface-mount component [patent_app_type] => utility [patent_app_number] => 14/724665 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 9117 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724665 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724665
Electronic device including soldered surface-mount component May 27, 2015 Issued
Array ( [id] => 11453194 [patent_doc_number] => 09576845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method for manufacturing a semiconductor device including a hollow structure around an electrode of a semiconductor element' [patent_app_type] => utility [patent_app_number] => 14/706852 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2279 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706852
Method for manufacturing a semiconductor device including a hollow structure around an electrode of a semiconductor element May 6, 2015 Issued
Array ( [id] => 10455483 [patent_doc_number] => 20150340498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/672385 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 21664 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672385
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Mar 29, 2015 Issued
Array ( [id] => 10455483 [patent_doc_number] => 20150340498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/672385 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 21664 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672385
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Mar 29, 2015 Issued
Array ( [id] => 10455483 [patent_doc_number] => 20150340498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/672385 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 21664 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672385
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Mar 29, 2015 Issued
Array ( [id] => 10455483 [patent_doc_number] => 20150340498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/672385 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 21664 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672385
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Mar 29, 2015 Issued
Array ( [id] => 10395113 [patent_doc_number] => 20150280120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'RESISTIVE RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/669279 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5246 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669279
Metal-oxide-based conductive-bridging random access memory (CBRAM) having the solid electrolyte doped with a second metal Mar 25, 2015 Issued
Array ( [id] => 11495428 [patent_doc_number] => 20170069613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/122590 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15122590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/122590
Power semiconductor module for an inverter circuit and method of manufacturing the same Mar 3, 2015 Issued
Array ( [id] => 10294747 [patent_doc_number] => 20150179745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Reduction of Edge Effects from Aspect Ratio Trapping' [patent_app_type] => utility [patent_app_number] => 14/629731 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629731 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629731
Reduction of edge effects from aspect ratio trapping Feb 23, 2015 Issued
Array ( [id] => 10255701 [patent_doc_number] => 20150140698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS' [patent_app_type] => utility [patent_app_number] => 14/607161 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4765 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607161 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607161
TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS Jan 27, 2015
Array ( [id] => 10255700 [patent_doc_number] => 20150140697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS' [patent_app_type] => utility [patent_app_number] => 14/607160 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4765 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607160
Test macro for use with a multi-patterning lithography process Jan 27, 2015 Issued
Array ( [id] => 11811541 [patent_doc_number] => 09716114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Array substrate with high qualified rate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/416766 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 24 [patent_no_of_words] => 7951 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14416766 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/416766
Array substrate with high qualified rate and manufacturing method thereof Dec 18, 2014 Issued
Array ( [id] => 11032737 [patent_doc_number] => 20160229693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'SELF-REMOVAL ANTI-STICTION COATING FOR BONDING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/564346 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564346
Self-removal anti-stiction coating for bonding process Dec 8, 2014 Issued
Array ( [id] => 10479572 [patent_doc_number] => 20150364589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'GRAPHENE-METAL BONDING STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE GRAPHENE-METAL BONDING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/533802 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10188 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533802 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533802
Graphene-metal bonding structure, method of manufacturing the same, and semiconductor device having the graphene-metal bonding structure Nov 4, 2014 Issued
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