Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18061754 [patent_doc_number] => 20220392841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/671088 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671088
Semiconductor device and method for fabricating semiconductor device Feb 13, 2022 Issued
Array ( [id] => 18919182 [patent_doc_number] => 11881471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/666732 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 9786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666732
Semiconductor device and manufacturing method thereof Feb 7, 2022 Issued
Array ( [id] => 18704751 [patent_doc_number] => 11791268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Tungsten structures and methods of forming the structures [patent_app_type] => utility [patent_app_number] => 17/666093 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7946 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666093
Tungsten structures and methods of forming the structures Feb 6, 2022 Issued
Array ( [id] => 17615367 [patent_doc_number] => 20220157647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/590260 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590260
Semiconductor structure and manufacturing method thereof Jan 31, 2022 Issued
Array ( [id] => 17599666 [patent_doc_number] => 20220149240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => LIGHT EMITTING DIODES CONTAINING DEACTIVATED REGIONS AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/583867 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583867
Light emitting diodes containing deactivated regions and methods of making the same Jan 24, 2022 Issued
Array ( [id] => 17599393 [patent_doc_number] => 20220148967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/583078 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583078
Interconnects having a portion without a liner material and related structures, devices, and methods Jan 23, 2022 Issued
Array ( [id] => 19444478 [patent_doc_number] => 12094767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Barrier layers for word line contacts in a three-dimensional NAND memory and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 17/580051 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 42 [patent_no_of_words] => 16032 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580051
Barrier layers for word line contacts in a three-dimensional NAND memory and fabrication methods thereof Jan 19, 2022 Issued
Array ( [id] => 19858231 [patent_doc_number] => 12261082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor devices with a nitrided capping layer [patent_app_type] => utility [patent_app_number] => 17/577707 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577707
Semiconductor devices with a nitrided capping layer Jan 17, 2022 Issued
Array ( [id] => 18950963 [patent_doc_number] => 11894269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Integrated assemblies and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/577031 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7045 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577031
Integrated assemblies and methods of forming integrated assemblies Jan 16, 2022 Issued
Array ( [id] => 18415996 [patent_doc_number] => 11670542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Stepped top via for via resistance reduction [patent_app_type] => utility [patent_app_number] => 17/570445 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7127 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570445
Stepped top via for via resistance reduction Jan 6, 2022 Issued
Array ( [id] => 18337645 [patent_doc_number] => 20230129594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME [patent_app_type] => utility [patent_app_number] => 17/566262 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566262
High aspect ratio via fill process employing selective metal deposition and structures formed by the same Dec 29, 2021 Issued
Array ( [id] => 19153839 [patent_doc_number] => 11978763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Electrical device comprising a 3D capacitor and a region surrounded by a through opening [patent_app_type] => utility [patent_app_number] => 17/551437 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4435 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551437
Electrical device comprising a 3D capacitor and a region surrounded by a through opening Dec 14, 2021 Issued
Array ( [id] => 18242671 [patent_doc_number] => 20230074982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A VIA AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/546470 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546470
Integrated circuit devices including a via and methods of forming the same Dec 8, 2021 Issued
Array ( [id] => 17583170 [patent_doc_number] => 20220140025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/545348 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545348
Display device and manufacturing method thereof Dec 7, 2021 Issued
Array ( [id] => 18424024 [patent_doc_number] => 20230178488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/643061 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643061
Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems Dec 6, 2021 Issued
Array ( [id] => 19720352 [patent_doc_number] => 12205895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Three-dimensional memory device having staircase structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/539834 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 10850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539834
Three-dimensional memory device having staircase structure and method for forming the same Nov 30, 2021 Issued
Array ( [id] => 17486082 [patent_doc_number] => 20220093586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL [patent_app_type] => utility [patent_app_number] => 17/540120 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540120
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material Nov 30, 2021 Issued
Array ( [id] => 18357818 [patent_doc_number] => 11646224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Method of fabricating semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/538044 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7473 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538044
Method of fabricating semiconductor structure Nov 29, 2021 Issued
Array ( [id] => 17486007 [patent_doc_number] => 20220093511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/537518 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537518
Method for manufacturing semiconductor device Nov 29, 2021 Issued
Array ( [id] => 17485952 [patent_doc_number] => 20220093456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VIA-FIRST PROCESS FOR CONNECTING A CONTACT AND A GATE ELECTRODE [patent_app_type] => utility [patent_app_number] => 17/533434 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533434
Via-first process for connecting a contact and a gate electrode Nov 22, 2021 Issued
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