Kim Kwok Chu

Array ( [id] => 18840187 [patent_doc_number] => 11848267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Functional component within interconnect structure of semiconductor device and method of forming same [patent_app_type] => utility [patent_app_number] => 17/532672 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17463692 [patent_doc_number] => 20220076998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR DEVICE HAVING A LANDING PAD WITH SPACERS [patent_app_type] => utility [patent_app_number] => 17/526118 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18363069 [patent_doc_number] => 20230144660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA [patent_app_type] => utility [patent_app_number] => 17/453670 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19964880 [patent_doc_number] => 12334399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Structures and methods for fabricating staircase regions of a three-dimensional NAND memory device [patent_app_type] => utility [patent_app_number] => 17/451188 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 1124 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19260943 [patent_doc_number] => 12021009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor device with plug structure [patent_app_type] => utility [patent_app_number] => 17/500456 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7748 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18782218 [patent_doc_number] => 11823984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Method for fabricating semiconductor device with plug structure [patent_app_type] => utility [patent_app_number] => 17/497775 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18126133 [patent_doc_number] => 20230011752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => LOCAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 17/496414 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17373733 [patent_doc_number] => 20220028785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => TOP VIA INTERCONNECT HAVING A LINE WITH A REDUCED BOTTOM DIMENSION [patent_app_type] => utility [patent_app_number] => 17/495980 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18284641 [patent_doc_number] => 20230100113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => BACKSIDE POWER RAILS [patent_app_type] => utility [patent_app_number] => 17/488389 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18081035 [patent_doc_number] => 20220406647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Reducing Oxidation by Etching Sacrificial and Protection Layer Separately [patent_app_type] => utility [patent_app_number] => 17/480201 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536661 [patent_doc_number] => 20220115270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/480746 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168482 [patent_doc_number] => 11984395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device containing bit lines separated by air gaps and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/479637 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 58 [patent_no_of_words] => 22754 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17339401 [patent_doc_number] => 20220005732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => TOP VIA WITH DAMASCENE LINE AND VIA [patent_app_type] => utility [patent_app_number] => 17/479346 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18967506 [patent_doc_number] => 11901287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Microelectronic devices with multiple step contacts extending to stepped tiers, and related systems and methods [patent_app_type] => utility [patent_app_number] => 17/476344 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 17070 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18250969 [patent_doc_number] => 20230078008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => VIA CD CONTROLLABLE TOP VIA STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/475463 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19199114 [patent_doc_number] => 11996363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Interconnect structure including a heat dissipation layer and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/473573 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17448711 [patent_doc_number] => 20220069216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => LOW RESISTANCE CROSSPOINT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/468167 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18241613 [patent_doc_number] => 20230073924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SELF-ALIGNED BURIED POWER RAIL CAP FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/466104 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17993250 [patent_doc_number] => 20220359287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => RECESSED CONTACTS AT LINE END AND METHODS FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/465499 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18226051 [patent_doc_number] => 20230065045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CONTACT FORMATION METHOD AND RELATED STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/461638 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461638 [rel_patent_id] =>[rel_patent_doc_number] =>)