Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18224169 [patent_doc_number] => 20230063163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CONTACT AND VIA STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/460653 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460653
Contact and via structures Aug 29, 2021 Issued
Array ( [id] => 18228533 [patent_doc_number] => 20230067527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING DEEP METAL LINE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/460859 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460859
Semiconductor structure having deep metal line and method for forming the semiconductor structure Aug 29, 2021 Issued
Array ( [id] => 18228306 [patent_doc_number] => 20230067300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ETCH METHOD FOR INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/461001 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461001
Etch method for interconnect structure Aug 29, 2021 Issued
Array ( [id] => 19842733 [patent_doc_number] => 12255133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/460211 [patent_app_country] => US [patent_app_date] => 2021-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460211
Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof Aug 27, 2021 Issued
Array ( [id] => 19376804 [patent_doc_number] => 12068385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Oxidation to mitigate dry etch and/or wet etch fluorine residue [patent_app_type] => utility [patent_app_number] => 17/446218 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446218
Oxidation to mitigate dry etch and/or wet etch fluorine residue Aug 26, 2021 Issued
Array ( [id] => 20111498 [patent_doc_number] => 12362234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Contact structure for semiconductor device [patent_app_type] => utility [patent_app_number] => 17/459799 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459799
Contact structure for semiconductor device Aug 26, 2021 Issued
Array ( [id] => 17764826 [patent_doc_number] => 20220238439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/458873 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458873
Semiconductor devices including via structures having a via portion and a barrier portion Aug 26, 2021 Issued
Array ( [id] => 18222699 [patent_doc_number] => 20230061693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => THREE-DIMENSIONAL (3D) INTERCONNECT STRUCTURES EMPLOYING VIA LAYER CONDUCTIVE STRUCTURES IN VIA LAYERS AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/410690 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410690
Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers and related fabrication methods Aug 23, 2021 Issued
Array ( [id] => 17262877 [patent_doc_number] => 20210375862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/403732 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403732
Buried channel semiconductor device and method for manufacturing the same Aug 15, 2021 Issued
Array ( [id] => 18920384 [patent_doc_number] => 11882694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/403181 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 10173 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403181
Semiconductor device and method for fabricating the same Aug 15, 2021 Issued
Array ( [id] => 17486005 [patent_doc_number] => 20220093509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => CONTACT WINDOW STRUCTURE, METAL PLUG AND FORMING METHOD THEREOF, AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/401461 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401461
Contact window structure, metal plug and forming method thereof, and semiconductor structure Aug 12, 2021 Issued
Array ( [id] => 17485950 [patent_doc_number] => 20220093454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => CONTACT WINDOW STRUCTURE AND METHOD FOR FORMING CONTACT WINDOW STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/396910 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396910
Contact window structure and method for forming contact window structure Aug 8, 2021 Issued
Array ( [id] => 19244497 [patent_doc_number] => 12014951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Semi-damascene structure with dielectric hardmask layer [patent_app_type] => utility [patent_app_number] => 17/390035 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 7725 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390035
Semi-damascene structure with dielectric hardmask layer Jul 29, 2021 Issued
Array ( [id] => 18548269 [patent_doc_number] => 11721629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Memory device including staircase structure having conductive pads [patent_app_type] => utility [patent_app_number] => 17/381991 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 13922 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381991
Memory device including staircase structure having conductive pads Jul 20, 2021 Issued
Array ( [id] => 17217732 [patent_doc_number] => 20210351070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING POLYSILICON STRUCTURES AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 17/380340 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380340
Semiconductor device including polysilicon structures and method of making Jul 19, 2021 Issued
Array ( [id] => 19567746 [patent_doc_number] => 12142525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Self-aligning spacer tight pitch via [patent_app_type] => utility [patent_app_number] => 17/378819 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4629 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/378819
Self-aligning spacer tight pitch via Jul 18, 2021 Issued
Array ( [id] => 17203494 [patent_doc_number] => 20210343589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => BARRIER-LESS PREFILLED VIA FORMATION [patent_app_type] => utility [patent_app_number] => 17/377541 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377541
Barrier-less prefilled via formation Jul 15, 2021 Issued
Array ( [id] => 19229662 [patent_doc_number] => 12009306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Three-dimensional memory device containing a capped isolation trench fill structure and methods of making the same [patent_app_type] => utility [patent_app_number] => 17/376490 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 75 [patent_no_of_words] => 22540 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376490
Three-dimensional memory device containing a capped isolation trench fill structure and methods of making the same Jul 14, 2021 Issued
Array ( [id] => 18967448 [patent_doc_number] => 11901228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Self-aligned scheme for semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/371416 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371416
Self-aligned scheme for semiconductor device and method of forming the same Jul 8, 2021 Issued
Array ( [id] => 18008485 [patent_doc_number] => 20220367252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Via-First Self-Aligned Interconnect Formation Process [patent_app_type] => utility [patent_app_number] => 17/371556 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371556
Via-first self-aligned interconnect formation process Jul 8, 2021 Issued
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