
Kim Kwok Chu
Examiner (ID: 4012)
| Most Active Art Unit | 2506 |
| Art Unit(s) | 2752, 2653, 2627, 2516, 2899, 2651, 2506 |
| Total Applications | 1354 |
| Issued Applications | 1184 |
| Pending Applications | 15 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17886541
[patent_doc_number] => 20220302019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => CAPACITOR AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/371641
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371641
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/371641 | Capacitor and method for forming the same | Jul 8, 2021 | Issued |
Array
(
[id] => 19016358
[patent_doc_number] => 11923300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Two-dimensional (2D) metal structure
[patent_app_type] => utility
[patent_app_number] => 17/371321
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 7348
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371321
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/371321 | Two-dimensional (2D) metal structure | Jul 8, 2021 | Issued |
Array
(
[id] => 18782308
[patent_doc_number] => 11824075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Photoelectric conversion device having isolation portions, and imaging system and moving body having photoelectric conversion device
[patent_app_type] => utility
[patent_app_number] => 17/368107
[patent_app_country] => US
[patent_app_date] => 2021-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 32
[patent_no_of_words] => 10774
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/368107 | Photoelectric conversion device having isolation portions, and imaging system and moving body having photoelectric conversion device | Jul 5, 2021 | Issued |
Array
(
[id] => 18097457
[patent_doc_number] => 20220415798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => INTERCONNECT STRUCTURE WITH HYBRID BARRIER LAYER
[patent_app_type] => utility
[patent_app_number] => 17/355566
[patent_app_country] => US
[patent_app_date] => 2021-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355566
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/355566 | Interconnect structure with hybrid barrier layer | Jun 22, 2021 | Issued |
Array
(
[id] => 19063177
[patent_doc_number] => 11942429
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Three-dimensional memory device and method of making thereof using double pitch word line formation
[patent_app_type] => utility
[patent_app_number] => 17/351811
[patent_app_country] => US
[patent_app_date] => 2021-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 109
[patent_figures_cnt] => 118
[patent_no_of_words] => 27408
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351811
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/351811 | Three-dimensional memory device and method of making thereof using double pitch word line formation | Jun 17, 2021 | Issued |
Array
(
[id] => 18068136
[patent_doc_number] => 20220399224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => BACKSIDE POWER RAIL INTEGRATION
[patent_app_type] => utility
[patent_app_number] => 17/342650
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342650
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342650 | Backside power rail integration | Jun 8, 2021 | Issued |
Array
(
[id] => 17917518
[patent_doc_number] => 20220319914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => Scalable Patterning Through Layer Expansion Process and Resulting Structures
[patent_app_type] => utility
[patent_app_number] => 17/329068
[patent_app_country] => US
[patent_app_date] => 2021-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6234
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329068
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/329068 | Scalable patterning through layer expansion process and resulting structures | May 23, 2021 | Issued |
Array
(
[id] => 18951130
[patent_doc_number] => 11894437
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Hybrid conductive structures
[patent_app_type] => utility
[patent_app_number] => 17/320553
[patent_app_country] => US
[patent_app_date] => 2021-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 6815
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320553
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/320553 | Hybrid conductive structures | May 13, 2021 | Issued |
Array
(
[id] => 18371867
[patent_doc_number] => 11652049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-16
[patent_title] => Semiconductor device and method of forming thereof
[patent_app_type] => utility
[patent_app_number] => 17/318327
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 10169
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318327
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/318327 | Semiconductor device and method of forming thereof | May 11, 2021 | Issued |
Array
(
[id] => 17564751
[patent_doc_number] => 20220128900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => PHOTOMASK, EXPOSURE APPARATUS, AND METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/306644
[patent_app_country] => US
[patent_app_date] => 2021-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4289
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306644
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/306644 | Photomask, exposure apparatus, and method of fabricating three-dimensional semiconductor memory device using the same | May 2, 2021 | Issued |
Array
(
[id] => 17986310
[patent_doc_number] => 20220352347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => SEMICONDUCTOR HAVING A SOURCE/DRAIN CONTACT WITH A SINGLE INNER SPACER
[patent_app_type] => utility
[patent_app_number] => 17/245695
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245695
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/245695 | Semiconductor having a source/drain contact with a single inner spacer | Apr 29, 2021 | Issued |
Array
(
[id] => 17963683
[patent_doc_number] => 20220344264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => DIELECTRIC ON WIRE STRUCTURE TO INCREASE PROCESSING WINDOW FOR OVERLYING VIA
[patent_app_type] => utility
[patent_app_number] => 17/236234
[patent_app_country] => US
[patent_app_date] => 2021-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11354
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236234
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/236234 | Dielectric on wire structure to increase processing window for overlying via | Apr 20, 2021 | Issued |
Array
(
[id] => 18175125
[patent_doc_number] => 11574842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Methods for forming conductive vias, and associated devices and systems
[patent_app_type] => utility
[patent_app_number] => 17/230833
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 5347
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230833
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230833 | Methods for forming conductive vias, and associated devices and systems | Apr 13, 2021 | Issued |
Array
(
[id] => 16995512
[patent_doc_number] => 20210233932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-29
[patent_title] => INTERCONNECT STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/228526
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228526
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/228526 | Interconnect structures of three-dimensional memory devices | Apr 11, 2021 | Issued |
Array
(
[id] => 17917597
[patent_doc_number] => 20220319993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/219188
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6992
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219188
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/219188 | Method of manufacturing semiconductor device and semiconductor devices | Mar 30, 2021 | Issued |
Array
(
[id] => 17917596
[patent_doc_number] => 20220319992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => PLASMA-DAMAGE-RESISTANT INTERCONNECT STRUCTURE AND METHODS FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/218435
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10645
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218435
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/218435 | Plasma-damage-resistant interconnect structure and methods for manufacturing the same | Mar 30, 2021 | Issued |
Array
(
[id] => 17011120
[patent_doc_number] => 20210242281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => GaN-BASED THRESHOLD SWITCHING DEVICE AND MEMORY DIODE
[patent_app_type] => utility
[patent_app_number] => 17/215282
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3325
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215282
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/215282 | GaN-based threshold switching device and memory diode | Mar 28, 2021 | Issued |
Array
(
[id] => 17738006
[patent_doc_number] => 20220223468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => SEMICONDUCTOR STRUCTURE AND ITS MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/595575
[patent_app_country] => US
[patent_app_date] => 2021-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595575
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/595575 | Semiconductor structure including a trench having a high aspect ratio formed by etching and its manufacturing method as applied to formation of a capacitor in the semiconductor structure | Mar 24, 2021 | Issued |
Array
(
[id] => 18669932
[patent_doc_number] => 11776844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Contact via structures of semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/211733
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4604
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211733
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211733 | Contact via structures of semiconductor devices | Mar 23, 2021 | Issued |
Array
(
[id] => 16951931
[patent_doc_number] => 20210210623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => Methods Of Forming NAND Cell Units
[patent_app_type] => utility
[patent_app_number] => 17/206324
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206324
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/206324 | Methods of forming NAND cell units | Mar 18, 2021 | Issued |