Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16578739 [patent_doc_number] => 20210013140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/031913 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031913
Semiconductor structure, package structure, and manufacturing method thereof Sep 24, 2020 Issued
Array ( [id] => 17486001 [patent_doc_number] => 20220093505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES [patent_app_type] => utility [patent_app_number] => 17/031825 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031825
VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES Sep 23, 2020 Abandoned
Array ( [id] => 17978671 [patent_doc_number] => 11495543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device capable of preventing an increase in the number of manufacturing steps relating to wiring and a method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/004234 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5494 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004234
Semiconductor device capable of preventing an increase in the number of manufacturing steps relating to wiring and a method for manufacturing the same Aug 26, 2020 Issued
Array ( [id] => 17448206 [patent_doc_number] => 20220068711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE HAVING A LANDING PAD WITH SPACERS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/002278 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002278
Semiconductor device having a landing pad with spacers and method for fabricating the same Aug 24, 2020 Issued
Array ( [id] => 17417072 [patent_doc_number] => 20220051976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => INTERCONNECTS INCLUDING DUAL-METAL VIAS [patent_app_type] => utility [patent_app_number] => 16/993340 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993340
Interconnects including dual-metal vias Aug 13, 2020 Issued
Array ( [id] => 16469764 [patent_doc_number] => 20200371301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => FIBER OPTICS PRINTED CIRCUIT BOARD ASSEMBLY SURFACE CLEANING AND ROUGHENING [patent_app_type] => utility [patent_app_number] => 16/993846 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993846
Fiber optics printed circuit board assembly surface cleaning and roughening Aug 13, 2020 Issued
Array ( [id] => 16471660 [patent_doc_number] => 20200373198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => METAL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/992055 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992055
Metal interconnect structure and method for fabricating the same Aug 11, 2020 Issued
Array ( [id] => 18073721 [patent_doc_number] => 11532561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Different via configurations for different via interface requirements [patent_app_type] => utility [patent_app_number] => 16/984884 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 22700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984884
Different via configurations for different via interface requirements Aug 3, 2020 Issued
Array ( [id] => 16936510 [patent_doc_number] => 20210202399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/945595 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945595
Semiconductor device and manufacturing method thereof Jul 30, 2020 Issued
Array ( [id] => 17373684 [patent_doc_number] => 20220028736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/936194 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936194 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936194
Semiconductor structure and method of manufacturing the same Jul 21, 2020 Issued
Array ( [id] => 17848125 [patent_doc_number] => 11437512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Buried channel metal-oxide-semiconductor field-effect transistor (MOSFET) and forming method thereof [patent_app_type] => utility [patent_app_number] => 16/934030 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934030
Buried channel metal-oxide-semiconductor field-effect transistor (MOSFET) and forming method thereof Jul 20, 2020 Issued
Array ( [id] => 17772415 [patent_doc_number] => 11404367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Method for forming semiconductor device with self-aligned conductive features [patent_app_type] => utility [patent_app_number] => 16/926942 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926942 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926942
Method for forming semiconductor device with self-aligned conductive features Jul 12, 2020 Issued
Array ( [id] => 16394725 [patent_doc_number] => 20200335666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/922827 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922827
Light emitting device Jul 6, 2020 Issued
Array ( [id] => 19213682 [patent_doc_number] => 12002754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Multi-height and multi-width interconnect line metallization for integrated circuit structures [patent_app_type] => utility [patent_app_number] => 16/911879 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6674 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911879
Multi-height and multi-width interconnect line metallization for integrated circuit structures Jun 24, 2020 Issued
Array ( [id] => 17470088 [patent_doc_number] => 11276571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Method of breaking through etch stop layer [patent_app_type] => utility [patent_app_number] => 16/907634 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 11130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/907634
Method of breaking through etch stop layer Jun 21, 2020 Issued
Array ( [id] => 16812105 [patent_doc_number] => 20210134660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 16/906615 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906615
Semiconductor device and method of manufacture using a contact etch stop layer (CESL) breakthrough process Jun 18, 2020 Issued
Array ( [id] => 16858497 [patent_doc_number] => 20210159242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/903514 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903514
Three-dimensional semiconductor memory devices Jun 16, 2020 Issued
Array ( [id] => 17668290 [patent_doc_number] => 11361994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Fully self-aligned interconnect structure [patent_app_type] => utility [patent_app_number] => 16/895338 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 7906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895338
Fully self-aligned interconnect structure Jun 7, 2020 Issued
Array ( [id] => 18219659 [patent_doc_number] => 11594609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Liner-free conductive structures [patent_app_type] => utility [patent_app_number] => 16/887577 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 6688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887577
Liner-free conductive structures May 28, 2020 Issued
Array ( [id] => 17010920 [patent_doc_number] => 20210242081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => Selective Hybrid Capping Layer for Metal Gates of Transistors [patent_app_type] => utility [patent_app_number] => 16/884837 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884837
Selective hybrid capping layer for metal gates of transistors May 26, 2020 Issued
Menu