Search

Kim Kwok Chu

Examiner (ID: 4012)

Most Active Art Unit
2506
Art Unit(s)
2752, 2653, 2627, 2516, 2899, 2651, 2506
Total Applications
1354
Issued Applications
1184
Pending Applications
15
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17730748 [patent_doc_number] => 11387149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor device and method for forming gate structure thereof [patent_app_type] => utility [patent_app_number] => 16/883933 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 66 [patent_no_of_words] => 11503 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883933
Semiconductor device and method for forming gate structure thereof May 25, 2020 Issued
Array ( [id] => 17668300 [patent_doc_number] => 11362004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => FinFET devices and methods of forming [patent_app_type] => utility [patent_app_number] => 16/876358 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 11532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876358
FinFET devices and methods of forming May 17, 2020 Issued
Array ( [id] => 17652650 [patent_doc_number] => 11355390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Interconnect strucutre with protective etch-stop [patent_app_type] => utility [patent_app_number] => 16/876465 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876465
Interconnect strucutre with protective etch-stop May 17, 2020 Issued
Array ( [id] => 17878586 [patent_doc_number] => 11450610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Vertical semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/876600 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 9120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876600 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876600
Vertical semiconductor devices May 17, 2020 Issued
Array ( [id] => 17424251 [patent_doc_number] => 11257712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Source/drain contact formation methods and devices [patent_app_type] => utility [patent_app_number] => 15/931111 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 7458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931111
Source/drain contact formation methods and devices May 12, 2020 Issued
Array ( [id] => 17438935 [patent_doc_number] => 11264275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Integrated assemblies and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 16/872598 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7018 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/872598
Integrated assemblies and methods of forming integrated assemblies May 11, 2020 Issued
Array ( [id] => 17623290 [patent_doc_number] => 11342355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Interconnect structures of three-dimensional memory devices [patent_app_type] => utility [patent_app_number] => 16/863006 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863006
Interconnect structures of three-dimensional memory devices Apr 29, 2020 Issued
Array ( [id] => 17254070 [patent_doc_number] => 11189568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Top via interconnect having a line with a reduced bottom dimension [patent_app_type] => utility [patent_app_number] => 16/861267 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5874 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861267
Top via interconnect having a line with a reduced bottom dimension Apr 28, 2020 Issued
Array ( [id] => 16858380 [patent_doc_number] => 20210159125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => STRAINED SEMICONDUCTOR DEVICE WITH IMPROVED NBTI AND A METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/856981 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856981
Strained semiconductor device with improved NBTI and a method of making the same Apr 22, 2020 Issued
Array ( [id] => 17174080 [patent_doc_number] => 20210327751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/851167 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851167
Etch stop layer removal for capacitance reduction in damascene top via integration Apr 16, 2020 Issued
Array ( [id] => 17623163 [patent_doc_number] => 11342227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Stacked transistor structures with asymmetrical terminal interconnects [patent_app_type] => utility [patent_app_number] => 16/832500 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832500
Stacked transistor structures with asymmetrical terminal interconnects Mar 26, 2020 Issued
Array ( [id] => 17112938 [patent_doc_number] => 20210293535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SELF-ALIGNED LIGHT ANGLE SENSOR USING THIN METAL SILICIDE ANODES [patent_app_type] => utility [patent_app_number] => 16/826257 [patent_app_country] => US [patent_app_date] => 2020-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826257
Self-aligned light angle sensor using thin metal silicide anodes Mar 21, 2020 Issued
Array ( [id] => 17366180 [patent_doc_number] => 11233213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Organic light emitting display device [patent_app_type] => utility [patent_app_number] => 16/825014 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8233 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825014
Organic light emitting display device Mar 19, 2020 Issued
Array ( [id] => 17100199 [patent_doc_number] => 20210287990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/820046 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820046
Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems Mar 15, 2020 Issued
Array ( [id] => 17559155 [patent_doc_number] => 11315877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems [patent_app_type] => utility [patent_app_number] => 16/817267 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14490 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817267
Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems Mar 11, 2020 Issued
Array ( [id] => 16316115 [patent_doc_number] => 20200294853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/806062 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806062
Semiconductor device and forming method thereof Mar 1, 2020 Issued
Array ( [id] => 17254027 [patent_doc_number] => 11189525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Via-first process for connecting a contact and a gate electrode [patent_app_type] => utility [patent_app_number] => 16/797375 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 16058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797375
Via-first process for connecting a contact and a gate electrode Feb 20, 2020 Issued
Array ( [id] => 16820135 [patent_doc_number] => 11004974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => Field effect transistors containing electric field assist layers at gate corners and method of making the same [patent_app_type] => utility [patent_app_number] => 16/791049 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 10568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791049
Field effect transistors containing electric field assist layers at gate corners and method of making the same Feb 13, 2020 Issued
Array ( [id] => 17025430 [patent_doc_number] => 20210249302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => STEPPED TOP VIA FOR VIA RESISTANCE REDUCTION [patent_app_type] => utility [patent_app_number] => 16/787240 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787240
Stepped top via for via resistance reduction Feb 10, 2020 Issued
Array ( [id] => 15939081 [patent_doc_number] => 20200161174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING POLYSILICON STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/773640 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773640
Method of forming semiconductor device including polysilicon structures Jan 26, 2020 Issued
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