Search

Kim Thanh Thi Tran

Examiner (ID: 8034, Phone: (571)270-1408 , Office: P/2612 )

Most Active Art Unit
2612
Art Unit(s)
2615, 2612, 2616, 2677, 2678, 2628
Total Applications
420
Issued Applications
318
Pending Applications
28
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20429372 [patent_doc_number] => 20250391465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER FOR READING DATA WITH IMPROVED SPEED, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE AND THE CONTROLLER [patent_app_type] => utility [patent_app_number] => 19/308716 [patent_app_country] => US [patent_app_date] => 2025-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19308716 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/308716
SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER FOR READING DATA WITH IMPROVED SPEED, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE AND THE CONTROLLER Aug 24, 2025 Pending
Array ( [id] => 20044595 [patent_doc_number] => 20250182817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => MULTI-PORT MEMORY DEVICE WITH BUILT-IN CONFIGURABLE LOGIC BLOCK TO PERFORM A PARALLEL COMPUTING OPERATION [patent_app_type] => utility [patent_app_number] => 18/943434 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943434
MULTI-PORT MEMORY DEVICE WITH BUILT-IN CONFIGURABLE LOGIC BLOCK TO PERFORM A PARALLEL COMPUTING OPERATION Nov 10, 2024 Pending
Array ( [id] => 20153152 [patent_doc_number] => 20250252990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => ADVANCED CLOCK SIGNAL DRIVERS AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/925340 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925340
ADVANCED CLOCK SIGNAL DRIVERS AND MEMORY SYSTEMS INCLUDING THE SAME Oct 23, 2024 Pending
Array ( [id] => 20396659 [patent_doc_number] => 20250372134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/922931 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/922931
SEMICONDUCTOR DEVICE Oct 21, 2024 Pending
Array ( [id] => 20572052 [patent_doc_number] => 20260065980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => TECHNIQUES FOR CREATING BETWEEN MARGIN DELAY IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/824183 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/824183
TECHNIQUES FOR CREATING BETWEEN MARGIN DELAY IN MEMORY DEVICES Sep 3, 2024 Pending
Array ( [id] => 20222732 [patent_doc_number] => 20250285663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => MEMORY CIRCUITS WITH REGISTER CIRCUTIS AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/790547 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790547
MEMORY CIRCUITS WITH REGISTER CIRCUTIS AND METHODS FOR OPERATING THE SAME Jul 30, 2024 Pending
Array ( [id] => 20488406 [patent_doc_number] => 20260024607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => MEMORY BUILT-IN-SELF-TEST (MBIST) WITH ENHANCED FAULT COUNTER [patent_app_type] => utility [patent_app_number] => 18/779378 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779378
MEMORY BUILT-IN-SELF-TEST (MBIST) WITH ENHANCED FAULT COUNTER Jul 21, 2024 Pending
Array ( [id] => 19803706 [patent_doc_number] => 20250069631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => DATA ALIGNMENT FOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/771448 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771448
DATA ALIGNMENT FOR MEMORY Jul 11, 2024 Pending
Array ( [id] => 20139201 [patent_doc_number] => 20250246245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/743956 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743956
MEMORY DEVICE AND OPERATION METHOD THEREOF, AND MEMORY SYSTEM Jun 13, 2024 Pending
Array ( [id] => 19618904 [patent_doc_number] => 20240404584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/678401 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678401 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678401
MEMORY DEVICE AND METHOD OF OPERATING THE SAME May 29, 2024 Pending
Array ( [id] => 19435724 [patent_doc_number] => 20240304222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/670302 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670302
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD May 20, 2024 Pending
Array ( [id] => 20291057 [patent_doc_number] => 20250316300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => CLOCK GATING OF FREE INDEX FLOP ARRAYS [patent_app_type] => utility [patent_app_number] => 18/667112 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667112
CLOCK GATING OF FREE INDEX FLOP ARRAYS May 16, 2024 Pending
Array ( [id] => 20367089 [patent_doc_number] => 20250356901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => DECISION FEEDBACK EQUALIZER SENSE AMPLIFIER CIRCUITS AND METHODS FOR DOUBLE DATA RATE NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/663824 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663824
DECISION FEEDBACK EQUALIZER SENSE AMPLIFIER CIRCUITS AND METHODS FOR DOUBLE DATA RATE NONVOLATILE MEMORY DEVICES May 13, 2024 Pending
Array ( [id] => 19893068 [patent_doc_number] => 20250118380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF, MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/635793 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635793
MEMORY DEVICE AND OPERATING METHOD THEREOF, MEMORY SYSTEM Apr 14, 2024 Pending
Array ( [id] => 19618921 [patent_doc_number] => 20240404601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => ALTERNATING BITLINE PAGE MAPPING WITH LINEAR WORDLINE RAMPING DURING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/624570 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624570
ALTERNATING BITLINE PAGE MAPPING WITH LINEAR WORDLINE RAMPING DURING A READ OPERATION Apr 1, 2024 Pending
Array ( [id] => 20028485 [patent_doc_number] => 20250166707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/623588 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623588
MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME Mar 31, 2024 Pending
Array ( [id] => 19803746 [patent_doc_number] => 20250069671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/614358 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614358
MEMORY CIRCUIT Mar 21, 2024 Pending
Array ( [id] => 20036057 [patent_doc_number] => 20250174279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => PAGE BUFFERS AND OPERATION METHODS THEREOF, AND MEMORY DEVICES AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/614163 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614163
PAGE BUFFERS AND OPERATION METHODS THEREOF, AND MEMORY DEVICES AND MEMORY SYSTEMS Mar 21, 2024 Pending
Array ( [id] => 19452412 [patent_doc_number] => 20240312542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/591856 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591856
SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM Feb 28, 2024 Pending
Array ( [id] => 20182137 [patent_doc_number] => 20250266095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => DYNAMIC WORD LINE RAMP UP KICK FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/443933 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443933
DYNAMIC WORD LINE RAMP UP KICK FOR MEMORY DEVICES Feb 15, 2024 Pending
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