Search

Kim Thanh Thi Tran

Examiner (ID: 8034, Phone: (571)270-1408 , Office: P/2612 )

Most Active Art Unit
2612
Art Unit(s)
2615, 2612, 2616, 2677, 2678, 2628
Total Applications
420
Issued Applications
318
Pending Applications
28
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19384337 [patent_doc_number] => 20240274207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/437664 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437664
MEMORY DEVICE Feb 8, 2024 Pending
Array ( [id] => 20167636 [patent_doc_number] => 20250259683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => ERASE BIAS SCHEME TO LOWER VERAMAX AND NAND CHIP-SIZE SHRINK [patent_app_type] => utility [patent_app_number] => 18/436345 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436345
ERASE BIAS SCHEME TO LOWER VERAMAX AND NAND CHIP-SIZE SHRINK Feb 7, 2024 Pending
Array ( [id] => 19305263 [patent_doc_number] => 20240233843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/425383 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425383
SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM Jan 28, 2024 Pending
Array ( [id] => 19406880 [patent_doc_number] => 20240290391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => COMPLEX PAGE ACCESS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/417899 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417899
COMPLEX PAGE ACCESS IN MEMORY DEVICES Jan 18, 2024 Pending
Array ( [id] => 19252473 [patent_doc_number] => 20240203470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHOD FOR OPERATING A DATA PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/535308 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535308
METHOD FOR OPERATING A DATA PROCESSING SYSTEM Dec 10, 2023 Issued
Array ( [id] => 19072013 [patent_doc_number] => 20240106439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => DELAY LOCKED LOOP, CLOCK SYNCHRONIZATION CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/528969 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528969
DELAY LOCKED LOOP, CLOCK SYNCHRONIZATION CIRCUIT AND MEMORY Dec 4, 2023 Abandoned
Array ( [id] => 19237075 [patent_doc_number] => 20240194270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DEBIASING SCHEME FOR PARTIAL BLOCK ERASE BASED ON WORD LINE GROUPS [patent_app_type] => utility [patent_app_number] => 18/528337 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528337 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528337
DEBIASING SCHEME FOR PARTIAL BLOCK ERASE BASED ON WORD LINE GROUPS Dec 3, 2023 Pending
Array ( [id] => 20028489 [patent_doc_number] => 20250166711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => ACHIEVING DIFFERENT HIGH VOLTAGES ON INDIVIDUAL BITLINES OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/510978 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510978
ACHIEVING DIFFERENT HIGH VOLTAGES ON INDIVIDUAL BITLINES OF A MEMORY DEVICE Nov 15, 2023 Pending
Array ( [id] => 19237043 [patent_doc_number] => 20240194238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH [patent_app_type] => utility [patent_app_number] => 18/507881 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507881
SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH Nov 12, 2023 Pending
Array ( [id] => 19986755 [patent_doc_number] => 20250124977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => COMPILED MULTI-PORT MEMORY [patent_app_type] => utility [patent_app_number] => 18/379957 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379957
COMPILED MULTI-PORT MEMORY Oct 12, 2023 Pending
Array ( [id] => 19574877 [patent_doc_number] => 20240379169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MEMORY AND OPERATION METHOD THEREOF, MEMORY SYSTEM AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/485084 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/485084
MEMORY AND OPERATION METHOD THEREOF, MEMORY SYSTEM AND ELECTRONIC DEVICE Oct 10, 2023 Pending
Array ( [id] => 19116135 [patent_doc_number] => 20240127885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => MEMORY DEVICE INCLUDING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/484089 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/484089
MEMORY DEVICE INCLUDING SEMICONDUCTOR ELEMENT Oct 9, 2023 Abandoned
Array ( [id] => 20482649 [patent_doc_number] => 12531125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Method and non-transitory computer-readable storage medium and apparatus for executing host commands [patent_app_type] => utility [patent_app_number] => 18/368890 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2406 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 460 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368890
Method and non-transitory computer-readable storage medium and apparatus for executing host commands Sep 14, 2023 Issued
Array ( [id] => 19054453 [patent_doc_number] => 20240096422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/459745 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459745 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459745
Storage device with word lines applied with respective voltage levels during different time periods Aug 31, 2023 Issued
Array ( [id] => 19007460 [patent_doc_number] => 20240071531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICES WITH PROGRAM VERIFY LEVELS BASED ON COMPENSATION VALUES [patent_app_type] => utility [patent_app_number] => 18/239193 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239193
Memory devices with program verify levels based on compensation values Aug 28, 2023 Issued
Array ( [id] => 19687721 [patent_doc_number] => 20250006266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => PROGRAMMING TECHNIQUES THAT UTILIZE ANALOG BITSCAN IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/232117 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232117
Programming techniques that utilize analog bitscan in a memory device Aug 8, 2023 Issued
Array ( [id] => 19687732 [patent_doc_number] => 20250006277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => ANALOG BITSCAN TECHNIQUES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/230972 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230972
ANALOG BITSCAN TECHNIQUES IN A MEMORY DEVICE Aug 6, 2023 Pending
Array ( [id] => 19757815 [patent_doc_number] => 20250046380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SHALLOW ERASE FOR ERASE POOL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/363470 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363470
SHALLOW ERASE FOR ERASE POOL MANAGEMENT Jul 31, 2023 Pending
Array ( [id] => 19406896 [patent_doc_number] => 20240290407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/363546 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363546
SEMICONDUCTOR MEMORY DEVICE Jul 31, 2023 Pending
Array ( [id] => 19384335 [patent_doc_number] => 20240274205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY DEVICE PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/357162 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357162
Memory device performing program operation and method of operating the same Jul 23, 2023 Issued
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