Search

Kimberley S. Wright

Examiner (ID: 10413, Phone: (571)270-3328 , Office: P/3637 )

Most Active Art Unit
3637
Art Unit(s)
3637
Total Applications
991
Issued Applications
671
Pending Applications
77
Abandoned Applications
264

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17708714 [patent_doc_number] => 20220208722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DIE BONDING METHOD WITH CORNER OR SIDE CONTACT WITHOUT IMPACT FORCE [patent_app_type] => utility [patent_app_number] => 17/492711 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492711
Die bonding method with corner or side contact without impact force Oct 3, 2021 Issued
Array ( [id] => 17523125 [patent_doc_number] => 20220108974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => METHOD OF FORMING A CHIP PACKAGE AND CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 17/491647 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491647
Method of forming a chip package and chip package Sep 30, 2021 Issued
Array ( [id] => 19679396 [patent_doc_number] => 12191269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Three-dimensional memory device and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/483121 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483121
Three-dimensional memory device and method for forming the same Sep 22, 2021 Issued
Array ( [id] => 19428257 [patent_doc_number] => 12087691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Semiconductor structures with backside gate contacts [patent_app_type] => utility [patent_app_number] => 17/480531 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 72 [patent_no_of_words] => 7777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480531
Semiconductor structures with backside gate contacts Sep 20, 2021 Issued
Array ( [id] => 18623786 [patent_doc_number] => 11756842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Daisy-chain seal ring structure [patent_app_type] => utility [patent_app_number] => 17/448002 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448002
Daisy-chain seal ring structure Sep 16, 2021 Issued
Array ( [id] => 18522075 [patent_doc_number] => 11711985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => System and method for superconducting multi-chip module [patent_app_type] => utility [patent_app_number] => 17/472821 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472821
System and method for superconducting multi-chip module Sep 12, 2021 Issued
Array ( [id] => 17509134 [patent_doc_number] => 20220102237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CHIP AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/473673 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473673
Chip and manufacturing method thereof, and electronic device Sep 12, 2021 Issued
Array ( [id] => 17886579 [patent_doc_number] => 20220302057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/468173 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468173
Semiconductor device and method for manufacturing the same Sep 6, 2021 Issued
Array ( [id] => 17917692 [patent_doc_number] => 20220320088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Gate Isolation for Multigate Device [patent_app_type] => utility [patent_app_number] => 17/466569 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466569
Gate isolation for multigate device Sep 2, 2021 Issued
Array ( [id] => 19951339 [patent_doc_number] => 12322710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Three-dimensional memory device with finned support pillar structures and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/462446 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 89 [patent_no_of_words] => 26126 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462446
Three-dimensional memory device with finned support pillar structures and method of forming the same Aug 30, 2021 Issued
Array ( [id] => 19314499 [patent_doc_number] => 12040325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Integrated circuit structure with a reduced amount of defects and methods for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/462709 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 87 [patent_no_of_words] => 13716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462709
Integrated circuit structure with a reduced amount of defects and methods for fabricating the same Aug 30, 2021 Issued
Array ( [id] => 18227262 [patent_doc_number] => 20230066256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/446460 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446460
Semiconductor device and manufacturing method thereof Aug 29, 2021 Issued
Array ( [id] => 18223603 [patent_doc_number] => 20230062597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/461312 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461312
Semiconductor device and forming method thereof Aug 29, 2021 Issued
Array ( [id] => 18221214 [patent_doc_number] => 20230060208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING TEST PAD AND BONDING PAD STRUCTURE FOR DIE CONNECTION AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/461764 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461764
Semiconductor package including test pad and bonding pad structure for die connection and methods for forming the same Aug 29, 2021 Issued
Array ( [id] => 19371685 [patent_doc_number] => 12063790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Structure and method for MRAM devices [patent_app_type] => utility [patent_app_number] => 17/460627 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460627
Structure and method for MRAM devices Aug 29, 2021 Issued
Array ( [id] => 17295403 [patent_doc_number] => 20210391242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Fan-Out Package Structure and Method [patent_app_type] => utility [patent_app_number] => 17/460626 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460626
Fan-out package structure and method Aug 29, 2021 Issued
Array ( [id] => 18891081 [patent_doc_number] => 11869859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Die stack and integrated device structure including improved bonding structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/460180 [patent_app_country] => US [patent_app_date] => 2021-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460180
Die stack and integrated device structure including improved bonding structure and methods of forming the same Aug 27, 2021 Issued
Array ( [id] => 18874768 [patent_doc_number] => 11862591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Conductive buffer layers for semiconductor die assemblies and associated systems and methods [patent_app_type] => utility [patent_app_number] => 17/411229 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7259 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411229
Conductive buffer layers for semiconductor die assemblies and associated systems and methods Aug 24, 2021 Issued
Array ( [id] => 18424050 [patent_doc_number] => 20230178514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => CHIP STACK PACKAGING STRUCTURE AND CHIP STACK PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 17/634081 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17634081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/634081
Chip stack packaging structure and chip stack packaging method Aug 4, 2021 Issued
Array ( [id] => 18292383 [patent_doc_number] => 11621256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/393934 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393934
Integrated circuit device Aug 3, 2021 Issued
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