Kimberley S. Wright

Array ( [id] => 20692160 [patent_doc_number] => 12622336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Bonding layer and process [patent_app_type] => utility [patent_app_number] => 18/320781 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 3189 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19575190 [patent_doc_number] => 20240379482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/316237 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19460192 [patent_doc_number] => 12100701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-24 [patent_title] => Hybrid system including photonic and electronic integrated circuits and cooling plate [patent_app_type] => utility [patent_app_number] => 18/142410 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 13357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20776949 [patent_doc_number] => 12660647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Edge fill for stacked structure [patent_app_type] => utility [patent_app_number] => 18/310293 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 2204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19206270 [patent_doc_number] => 20240178169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING BONDING PAD [patent_app_type] => utility [patent_app_number] => 18/307816 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18729438 [patent_doc_number] => 20230343734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => EXPANSION CONTROLLED STRUCTURE FOR DIRECT BONDING AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/305149 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555223 [patent_doc_number] => 20230253240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => Dummy Fin Structures and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 18/302428 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500404 [patent_doc_number] => 20240339422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SUPPORTING SEALANT LAYER STRUCTURE FOR STACKED DIE APPLICATION [patent_app_type] => utility [patent_app_number] => 18/298064 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18540863 [patent_doc_number] => 20230245974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FOR HIGH PERFORMANCE MICROPROCESSORS [patent_app_type] => utility [patent_app_number] => 18/131829 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19428234 [patent_doc_number] => 12087668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Semiconductor package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/194792 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19484185 [patent_doc_number] => 20240332227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING LOW-K DIELECTRIC MATERIAL [patent_app_type] => utility [patent_app_number] => 18/194544 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19567809 [patent_doc_number] => 12142588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/126205 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 10451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19101064 [patent_doc_number] => 20240120292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => STACK PACKAGE INCLUDING INSERT DIE FOR REINFORCEMENT [patent_app_type] => utility [patent_app_number] => 18/186274 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19452821 [patent_doc_number] => 20240312951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SYSTEM AND METHOD FOR BONDING TRANSPARENT CONDUCTOR SUBSTRATES [patent_app_type] => utility [patent_app_number] => 18/183768 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18473261 [patent_doc_number] => 20230207549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/179056 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19436095 [patent_doc_number] => 20240304593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => DIRECT BONDING METHODS AND STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/179126 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18586035 [patent_doc_number] => 20230268300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/173690 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19823528 [patent_doc_number] => 20250081735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => Display Panel and Display Device [patent_app_type] => utility [patent_app_number] => 18/288914 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18288914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19087902 [patent_doc_number] => 20240114703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => STRUCTURE AND FORMATION METHOD OF PACKAGE WITH HYBRID INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 18/163412 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19444569 [patent_doc_number] => 12094860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/162671 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162671 [rel_patent_id] =>[rel_patent_doc_number] =>)