Search

Kimberley S. Wright

Examiner (ID: 10413, Phone: (571)270-3328 , Office: P/3637 )

Most Active Art Unit
3637
Art Unit(s)
3637
Total Applications
991
Issued Applications
671
Pending Applications
77
Abandoned Applications
264

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848939 [patent_doc_number] => 20230411343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/883595 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883595
Manufacturing method of semiconductor structure Aug 7, 2022 Issued
Array ( [id] => 18024379 [patent_doc_number] => 20220375878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => SEAL RING FOR HYBRID-BOND [patent_app_type] => utility [patent_app_number] => 17/881739 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881739
Seal ring for hybrid-bond Aug 4, 2022 Issued
Array ( [id] => 19951290 [patent_doc_number] => 12322661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Shifted via-chain electrical-test measurements for hybrid bonding alignment correlation [patent_app_type] => utility [patent_app_number] => 17/876176 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876176
Shifted via-chain electrical-test measurements for hybrid bonding alignment correlation Jul 27, 2022 Issued
Array ( [id] => 18943494 [patent_doc_number] => 20240038633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => EMBEDDED COOLING SYSTEMS AND METHODS OF MANUFACTURING EMBEDDED COOLING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/876376 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876376
Embedded cooling systems and methods of manufacturing embedded cooling systems Jul 27, 2022 Issued
Array ( [id] => 18528734 [patent_doc_number] => 11715738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/875034 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 10970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875034
Semiconductor device and manufacturing method thereof Jul 26, 2022 Issued
Array ( [id] => 18833899 [patent_doc_number] => 20230402426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/874332 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874332
Manufacturing method of semiconductor structure Jul 26, 2022 Issued
Array ( [id] => 20245976 [patent_doc_number] => 12426321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Transistor gate structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/867804 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 8104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867804
Transistor gate structures and methods of forming the same Jul 18, 2022 Issued
Array ( [id] => 20776987 [patent_doc_number] => 12660686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Packaged semiconductor devices and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/813411 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6882 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813411
Packaged semiconductor devices and methods of forming the same Jul 18, 2022 Issued
Array ( [id] => 19926350 [patent_doc_number] => 12300645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Connector and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/866209 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 54 [patent_no_of_words] => 7592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866209
Connector and method for forming the same Jul 14, 2022 Issued
Array ( [id] => 20146818 [patent_doc_number] => 12381165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/863648 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 35 [patent_no_of_words] => 8920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863648 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863648
Semiconductor structure and method of manufacturing the same Jul 12, 2022 Issued
Array ( [id] => 19765920 [patent_doc_number] => 12224221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Packaging method and package structure [patent_app_type] => utility [patent_app_number] => 17/863400 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3928 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863400
Packaging method and package structure Jul 12, 2022 Issued
Array ( [id] => 17963693 [patent_doc_number] => 20220344274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/811649 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811649
Interconnection structure, fabricating method thereof, and semiconductor device using the same Jul 10, 2022 Issued
Array ( [id] => 18898606 [patent_doc_number] => 20240014091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Thermal Structure for Semiconductor Device and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/861556 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861556
Thermal structure for semiconductor device and method of forming the same Jul 10, 2022 Issued
Array ( [id] => 18865995 [patent_doc_number] => 20230420432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES [patent_app_type] => utility [patent_app_number] => 17/846173 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846173
Package architecture of photonic system with vertically stacked dies having planarized edges Jun 21, 2022 Issued
Array ( [id] => 18712923 [patent_doc_number] => 20230335556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => STEP-STACKED NANOWIRE CMOS STRUCTURE FOR LOW POWER LOGIC DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/841510 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841510
Step-stacked nanowire CMOS structure for low power logic device and method of manufacturing the same Jun 14, 2022 Issued
Array ( [id] => 18833886 [patent_doc_number] => 20230402413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING HYBRID BONDING PAD [patent_app_type] => utility [patent_app_number] => 17/840081 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840081
Method of manufacturing semiconductor structure having hybrid bonding pad Jun 13, 2022 Issued
Array ( [id] => 19123947 [patent_doc_number] => 11967948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink [patent_app_type] => utility [patent_app_number] => 17/839386 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 25475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839386
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink Jun 12, 2022 Issued
Array ( [id] => 17886612 [patent_doc_number] => 20220302090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MICROELECTRONIC DEVICE ASSEMBLIES AND PACKAGES INCLUDING MULTIPLE DEVICE STACKS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/805818 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805818
Microelectronic device assemblies and packages including multiple device stacks and related methods Jun 6, 2022 Issued
Array ( [id] => 18669942 [patent_doc_number] => 11776854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Semiconductor structure with hybrid nanostructures [patent_app_type] => utility [patent_app_number] => 17/827219 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 43 [patent_no_of_words] => 13629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827219
Semiconductor structure with hybrid nanostructures May 26, 2022 Issued
Array ( [id] => 18211072 [patent_doc_number] => 20230057334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => Polarizer-Free Displays [patent_app_type] => utility [patent_app_number] => 17/824787 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824787
Polarizer-free displays May 24, 2022 Issued
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