Search

Kimberly Ballard

Examiner (ID: 1514, Phone: (571)272-2150 , Office: P/1649 )

Most Active Art Unit
1649
Art Unit(s)
1649
Total Applications
837
Issued Applications
382
Pending Applications
80
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8314910 [patent_doc_number] => 20120191923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'OUTPUTTING A PARTICULAR DATA QUANTIZATION FROM MEMORY' [patent_app_type] => utility [patent_app_number] => 13/010589 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9666 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13010589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010589
Outputting a particular data quantization from memory Jan 19, 2011 Issued
Array ( [id] => 6044801 [patent_doc_number] => 20110205796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND SYSTEM PERFORMING REPAIR OPERATION FOR DEFECTIVE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/008431 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20110205796.pdf [firstpage_image] =>[orig_patent_app_number] => 13008431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008431
Nonvolatile memory device and system performing repair operation for defective memory cell Jan 17, 2011 Issued
Array ( [id] => 8803560 [patent_doc_number] => 08441840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Semiconductor device and data processing system' [patent_app_type] => utility [patent_app_number] => 13/006109 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9244 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13006109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006109
Semiconductor device and data processing system Jan 12, 2011 Issued
Array ( [id] => 8288525 [patent_doc_number] => 20120176850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'COLUMN ADDRESS STROBE WRITE LATENCY (CWL) CALIBRATION IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/985481 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985481
Column address strobe write latency (CWL) calibration in a memory system Jan 5, 2011 Issued
Array ( [id] => 8544867 [patent_doc_number] => 08320164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Static random access memory with data controlled power supply' [patent_app_type] => utility [patent_app_number] => 12/985289 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4554 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985289
Static random access memory with data controlled power supply Jan 4, 2011 Issued
Array ( [id] => 8726922 [patent_doc_number] => 08406058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Read only memory and operating method thereof' [patent_app_type] => utility [patent_app_number] => 12/983985 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2716 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983985
Read only memory and operating method thereof Jan 3, 2011 Issued
Array ( [id] => 8207714 [patent_doc_number] => 20120127813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'DEVICE AND METHOD FOR STORING ERROR INFORMATION OF MEMORY' [patent_app_type] => utility [patent_app_number] => 12/982705 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127813.pdf [firstpage_image] =>[orig_patent_app_number] => 12982705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982705
Device and method for storing error information of memory Dec 29, 2010 Issued
Array ( [id] => 8714674 [patent_doc_number] => 08400817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/979039 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 56 [patent_no_of_words] => 27879 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979039 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979039
Semiconductor device Dec 26, 2010 Issued
Array ( [id] => 8739734 [patent_doc_number] => 08411513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Techniques for providing a semiconductor memory device having hierarchical bit lines' [patent_app_type] => utility [patent_app_number] => 12/974939 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974939 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974939
Techniques for providing a semiconductor memory device having hierarchical bit lines Dec 20, 2010 Issued
Array ( [id] => 7536496 [patent_doc_number] => 08050135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/971723 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3630 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/050/08050135.pdf [firstpage_image] =>[orig_patent_app_number] => 12971723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971723
Semiconductor memory device Dec 16, 2010 Issued
Array ( [id] => 8739722 [patent_doc_number] => 08411502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Flash memory device using adaptive program verification scheme and related method of operation' [patent_app_type] => utility [patent_app_number] => 12/963867 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 45 [patent_no_of_words] => 17520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963867
Flash memory device using adaptive program verification scheme and related method of operation Dec 8, 2010 Issued
Array ( [id] => 8573202 [patent_doc_number] => 08339855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Reverse order page writing in flash memories' [patent_app_type] => utility [patent_app_number] => 12/961431 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8686 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961431 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961431
Reverse order page writing in flash memories Dec 5, 2010 Issued
Array ( [id] => 8226346 [patent_doc_number] => 20120140551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL' [patent_app_type] => utility [patent_app_number] => 12/959883 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959883
Static random access memory (SRAM) write assist circuit with leakage suppression and level control Dec 2, 2010 Issued
Array ( [id] => 8376691 [patent_doc_number] => 08259492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Method of reading dual-bit memory cell' [patent_app_type] => utility [patent_app_number] => 12/914020 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3744 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914020
Method of reading dual-bit memory cell Oct 27, 2010 Issued
Array ( [id] => 8677012 [patent_doc_number] => 08385136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Memory circuit and method of operating the same' [patent_app_type] => utility [patent_app_number] => 12/913087 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913087 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913087
Memory circuit and method of operating the same Oct 26, 2010 Issued
Array ( [id] => 8284237 [patent_doc_number] => 08218347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Stacked memory device having a scalable bandwidth interface' [patent_app_type] => utility [patent_app_number] => 12/902599 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12902599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/902599
Stacked memory device having a scalable bandwidth interface Oct 11, 2010 Issued
12/895094 SEMICONDUCTOR MEMORY DEVICE AND MODULE FOR HIGH FREQUENCY OPERATION Sep 29, 2010 Abandoned
Array ( [id] => 8544861 [patent_doc_number] => 08320158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/882685 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4221 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12882685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/882685
Nonvolatile semiconductor memory device Sep 14, 2010 Issued
Array ( [id] => 6093207 [patent_doc_number] => 20110002157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'RESISTANCE CHANGE TYPE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/881919 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15006 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20110002157.pdf [firstpage_image] =>[orig_patent_app_number] => 12881919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881919
RESISTANCE CHANGE TYPE MEMORY Sep 13, 2010 Abandoned
Array ( [id] => 6006086 [patent_doc_number] => 20110058445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/876703 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10564 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20110058445.pdf [firstpage_image] =>[orig_patent_app_number] => 12876703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876703
Latency counter, semiconductor memory device including the same, and data processing system Sep 6, 2010 Issued
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