Search

Kimberly Ballard

Examiner (ID: 1514, Phone: (571)272-2150 , Office: P/1649 )

Most Active Art Unit
1649
Art Unit(s)
1649
Total Applications
837
Issued Applications
382
Pending Applications
80
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6259279 [patent_doc_number] => 20100296347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Method of erasing device including complementary nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/662989 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 38180 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296347.pdf [firstpage_image] =>[orig_patent_app_number] => 12662989 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662989
Method of erasing a memory device including complementary nonvolatile memory devices May 13, 2010 Issued
Array ( [id] => 8550651 [patent_doc_number] => 08325539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Semiconductor memory device having physically shared data path and test device for the same' [patent_app_type] => utility [patent_app_number] => 12/773177 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6784 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12773177 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773177
Semiconductor memory device having physically shared data path and test device for the same May 3, 2010 Issued
Array ( [id] => 4625605 [patent_doc_number] => 08004911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Memory system, memory device, and output data strobe signal generating method' [patent_app_type] => utility [patent_app_number] => 12/662720 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6945 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004911.pdf [firstpage_image] =>[orig_patent_app_number] => 12662720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662720
Memory system, memory device, and output data strobe signal generating method Apr 28, 2010 Issued
Array ( [id] => 6508392 [patent_doc_number] => 20100202213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Current-Mode Sense Amplifying Method' [patent_app_type] => utility [patent_app_number] => 12/767418 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3881 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202213.pdf [firstpage_image] =>[orig_patent_app_number] => 12767418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767418
Current-mode sense amplifying method Apr 25, 2010 Issued
Array ( [id] => 6374836 [patent_doc_number] => 20100315879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'PAGE BUFFER OF NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING PROGRAM VERIFICATION OPERATION USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/764331 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4777 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315879.pdf [firstpage_image] =>[orig_patent_app_number] => 12764331 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764331
Page buffer of nonvolatile memory device and method of performing program verification operation using the same Apr 20, 2010 Issued
Array ( [id] => 8423203 [patent_doc_number] => 08279693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Programmable tracking circuit for tracking semiconductor memory read current' [patent_app_type] => utility [patent_app_number] => 12/757485 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8010 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757485
Programmable tracking circuit for tracking semiconductor memory read current Apr 8, 2010 Issued
Array ( [id] => 8573201 [patent_doc_number] => 08339854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Nonvolatile memory device and data randomizing method thereof' [patent_app_type] => utility [patent_app_number] => 12/752255 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4394 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12752255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752255
Nonvolatile memory device and data randomizing method thereof Mar 31, 2010 Issued
Array ( [id] => 6331925 [patent_doc_number] => 20100246308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/732845 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2584 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246308.pdf [firstpage_image] =>[orig_patent_app_number] => 12732845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732845
Semiconductor storage device and control methods thereof Mar 25, 2010 Issued
Array ( [id] => 6289659 [patent_doc_number] => 20100238752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/726647 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3039 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20100238752.pdf [firstpage_image] =>[orig_patent_app_number] => 12726647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726647
Semiconductor integrated circuit Mar 17, 2010 Issued
Array ( [id] => 4601696 [patent_doc_number] => 07978535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Data input/output circuit and method of semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/722734 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5531 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978535.pdf [firstpage_image] =>[orig_patent_app_number] => 12722734 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722734
Data input/output circuit and method of semiconductor memory apparatus Mar 11, 2010 Issued
Array ( [id] => 8167443 [patent_doc_number] => 08174901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/721553 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8089 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174901.pdf [firstpage_image] =>[orig_patent_app_number] => 12721553 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721553
Semiconductor integrated circuit device Mar 9, 2010 Issued
Array ( [id] => 8117361 [patent_doc_number] => 08159897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Two levels of voltage regulation supplied for logic and data programming voltage of a memory device' [patent_app_type] => utility [patent_app_number] => 12/715979 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 17419 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159897.pdf [firstpage_image] =>[orig_patent_app_number] => 12715979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715979
Two levels of voltage regulation supplied for logic and data programming voltage of a memory device Mar 1, 2010 Issued
Array ( [id] => 7990449 [patent_doc_number] => 08077528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Low couple effect bit-line voltage generator' [patent_app_type] => utility [patent_app_number] => 12/715504 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3347 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/077/08077528.pdf [firstpage_image] =>[orig_patent_app_number] => 12715504 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715504
Low couple effect bit-line voltage generator Mar 1, 2010 Issued
Array ( [id] => 6411931 [patent_doc_number] => 20100149875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Nonvolatile Semiconductor Memory Device' [patent_app_type] => utility [patent_app_number] => 12/714750 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5989 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20100149875.pdf [firstpage_image] =>[orig_patent_app_number] => 12714750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714750
Nonvolatile semiconductor memory device Feb 28, 2010 Issued
Array ( [id] => 6520293 [patent_doc_number] => 20100220524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'MAGNETIC BOOSTER FOR MAGNETIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 12/714401 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220524.pdf [firstpage_image] =>[orig_patent_app_number] => 12714401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714401
Magnetic booster for magnetic random access memory Feb 25, 2010 Issued
Array ( [id] => 8330083 [patent_doc_number] => 08238155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Multilevel memory cell operation' [patent_app_type] => utility [patent_app_number] => 12/703540 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 14412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703540
Multilevel memory cell operation Feb 9, 2010 Issued
Array ( [id] => 5960724 [patent_doc_number] => 20110185111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Systems and Methods for Extended Life Multi-Bit Memory Cells' [patent_app_type] => utility [patent_app_number] => 12/691819 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185111.pdf [firstpage_image] =>[orig_patent_app_number] => 12691819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691819
Systems and methods for extended life multi-bit memory cells Jan 21, 2010 Issued
Array ( [id] => 4625617 [patent_doc_number] => 08004923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Semiconductor device including internal voltage generation circuit' [patent_app_type] => utility [patent_app_number] => 12/683838 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 11175 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004923.pdf [firstpage_image] =>[orig_patent_app_number] => 12683838 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/683838
Semiconductor device including internal voltage generation circuit Jan 6, 2010 Issued
Array ( [id] => 6316624 [patent_doc_number] => 20100195422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/648851 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195422.pdf [firstpage_image] =>[orig_patent_app_number] => 12648851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648851
Semiconductor integrated circuit and method for controlling the same Dec 28, 2009 Issued
Array ( [id] => 6470471 [patent_doc_number] => 20100091583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'MEMORY DEVICE HAVING LATCH FOR CHARGING OR DISCHARGING DATA INPUT/OUTPUT LINE' [patent_app_type] => utility [patent_app_number] => 12/640883 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5643 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091583.pdf [firstpage_image] =>[orig_patent_app_number] => 12640883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640883
Memory device having latch for charging or discharging data input/output line Dec 16, 2009 Issued
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