Search

Kimberly Ballard

Examiner (ID: 1514, Phone: (571)272-2150 , Office: P/1649 )

Most Active Art Unit
1649
Art Unit(s)
1649
Total Applications
837
Issued Applications
382
Pending Applications
80
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6069269 [patent_doc_number] => 20110044118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Semiconductor Device having variable parameter selection based on temperature and test method' [patent_app_type] => utility [patent_app_number] => 12/635533 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13537 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20110044118.pdf [firstpage_image] =>[orig_patent_app_number] => 12635533 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/635533
Semiconductor device having variable parameter selection based on temperature and test method Dec 9, 2009 Issued
Array ( [id] => 6421073 [patent_doc_number] => 20100142245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/591711 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8612 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142245.pdf [firstpage_image] =>[orig_patent_app_number] => 12591711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591711
Semiconductor device Nov 29, 2009 Issued
Array ( [id] => 6312717 [patent_doc_number] => 20100070801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'MAINTENANCE OPERATIONS FOR MULTI-LEVEL DATA STORAGE CELLS' [patent_app_type] => utility [patent_app_number] => 12/624157 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070801.pdf [firstpage_image] =>[orig_patent_app_number] => 12624157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624157
Maintenance operations for multi-level data storage cells Nov 22, 2009 Issued
Array ( [id] => 6218942 [patent_doc_number] => 20100054037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'FLASH MEMORY DEVICE WITH MULTI LEVEL CELL AND BURST ACCESS METHOD THEREIN' [patent_app_type] => utility [patent_app_number] => 12/615374 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4586 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054037.pdf [firstpage_image] =>[orig_patent_app_number] => 12615374 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615374
Flash memory device with multi level cell and burst access method therein Nov 9, 2009 Issued
Array ( [id] => 6123461 [patent_doc_number] => 20110085391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Memory with improved read stability' [patent_app_type] => utility [patent_app_number] => 12/591127 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085391.pdf [firstpage_image] =>[orig_patent_app_number] => 12591127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591127
Memory with improved read stability Nov 8, 2009 Issued
Array ( [id] => 4625615 [patent_doc_number] => 08004921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Memory device, memory controller and memory system' [patent_app_type] => utility [patent_app_number] => 12/612247 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 184 [patent_figures_cnt] => 190 [patent_no_of_words] => 76721 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004921.pdf [firstpage_image] =>[orig_patent_app_number] => 12612247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612247
Memory device, memory controller and memory system Nov 3, 2009 Issued
Array ( [id] => 6276692 [patent_doc_number] => 20100118610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/610703 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118610.pdf [firstpage_image] =>[orig_patent_app_number] => 12610703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610703
Nonvolatile semiconductor memory device Nov 1, 2009 Issued
Array ( [id] => 5942530 [patent_doc_number] => 20110103150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/610781 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7985 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20110103150.pdf [firstpage_image] =>[orig_patent_app_number] => 12610781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610781
Non-volatile memory with predictive programming Nov 1, 2009 Issued
Array ( [id] => 8593362 [patent_doc_number] => 08351239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Dynamic sense current supply circuit and associated method for reading and characterizing a resistive memory array' [patent_app_type] => utility [patent_app_number] => 12/604915 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6340 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12604915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604915
Dynamic sense current supply circuit and associated method for reading and characterizing a resistive memory array Oct 22, 2009 Issued
Array ( [id] => 8411422 [patent_doc_number] => 08274824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-25 [patent_title] => 'High-performance CMOS-compatible non-volatile memory cell and related method' [patent_app_type] => utility [patent_app_number] => 12/589333 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4658 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12589333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/589333
High-performance CMOS-compatible non-volatile memory cell and related method Oct 21, 2009 Issued
Array ( [id] => 8295780 [patent_doc_number] => 08223574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Techniques for block refreshing a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/580171 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 15213 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12580171 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580171
Techniques for block refreshing a semiconductor memory device Oct 14, 2009 Issued
Array ( [id] => 8330097 [patent_doc_number] => 08238166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Methods of programming and reading single-level trapped-charge memory cells using second-bit threshold detection' [patent_app_type] => utility [patent_app_number] => 12/577687 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 7717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12577687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577687
Methods of programming and reading single-level trapped-charge memory cells using second-bit threshold detection Oct 11, 2009 Issued
Array ( [id] => 6469982 [patent_doc_number] => 20100091539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/576561 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6814 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091539.pdf [firstpage_image] =>[orig_patent_app_number] => 12576561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576561
Solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same Oct 8, 2009 Issued
Array ( [id] => 8550669 [patent_doc_number] => 08325556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Sequencing decoder circuit' [patent_app_type] => utility [patent_app_number] => 12/575055 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575055 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575055
Sequencing decoder circuit Oct 6, 2009 Issued
Array ( [id] => 6342992 [patent_doc_number] => 20100020607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION' [patent_app_type] => utility [patent_app_number] => 12/574079 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3731 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20100020607.pdf [firstpage_image] =>[orig_patent_app_number] => 12574079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574079
Method and apparatus for adaptive memory cell overerase compensation Oct 5, 2009 Issued
Array ( [id] => 8234105 [patent_doc_number] => 08199551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/570619 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 15109 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/199/08199551.pdf [firstpage_image] =>[orig_patent_app_number] => 12570619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570619
Semiconductor device Sep 29, 2009 Issued
Array ( [id] => 6603033 [patent_doc_number] => 20100309737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/568689 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5894 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309737.pdf [firstpage_image] =>[orig_patent_app_number] => 12568689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568689
Signal adjusting system and signal adjusting method Sep 28, 2009 Issued
Array ( [id] => 6368061 [patent_doc_number] => 20100080032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/564933 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080032.pdf [firstpage_image] =>[orig_patent_app_number] => 12564933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564933
SEMICONDUCTOR DEVICE Sep 22, 2009 Abandoned
Array ( [id] => 6361082 [patent_doc_number] => 20100073988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/565477 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6221 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073988.pdf [firstpage_image] =>[orig_patent_app_number] => 12565477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565477
Nonvolatile semiconductor storage device Sep 22, 2009 Issued
Array ( [id] => 8234100 [patent_doc_number] => 08199556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Methods of reading and using memory cells' [patent_app_type] => utility [patent_app_number] => 12/564265 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4598 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/199/08199556.pdf [firstpage_image] =>[orig_patent_app_number] => 12564265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564265
Methods of reading and using memory cells Sep 21, 2009 Issued
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