Search

Kimberly Chong

Examiner (ID: 7079, Phone: (571)272-3111 , Office: P/1674 )

Most Active Art Unit
1635
Art Unit(s)
1636, 1635, 1674
Total Applications
2004
Issued Applications
1153
Pending Applications
206
Abandoned Applications
674

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15090183 [patent_doc_number] => 20190339902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => REDUCING READ ERRORS BY PERFORMING MITIGATION READS TO BLOCKS OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/969431 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969431
Reducing read errors by performing mitigation reads to blocks of non-volatile memory May 1, 2018 Issued
Array ( [id] => 15486433 [patent_doc_number] => 10558567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-11 [patent_title] => Storage device embedded strand architecture [patent_app_type] => utility [patent_app_number] => 15/962660 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3245 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962660
Storage device embedded strand architecture Apr 24, 2018 Issued
Array ( [id] => 15027833 [patent_doc_number] => 20190324921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => OPTIMIZING CACHE PERFORMANCE WITH PROBABILISTIC MODEL [patent_app_type] => utility [patent_app_number] => 15/961402 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15961402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/961402
Optimizing cache performance with probabilistic model Apr 23, 2018 Issued
Array ( [id] => 13361539 [patent_doc_number] => 20180232309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => Computing Apparatus, Node Device, and Server [patent_app_type] => utility [patent_app_number] => 15/954002 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/954002
Computing apparatus, node device, and server Apr 15, 2018 Issued
Array ( [id] => 13497073 [patent_doc_number] => 20180300079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => METHODS OF ACCESSING MEMORY CELLS, METHODS OF DISTRIBUTING MEMORY REQUESTS, SYSTEMS, AND MEMORY CONTROLLERS [patent_app_type] => utility [patent_app_number] => 15/918178 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/918178
Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers Mar 11, 2018 Issued
Array ( [id] => 13568833 [patent_doc_number] => 20180335964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => COLLISION DETECTION AT MULTI-NODE STORAGE SITES [patent_app_type] => utility [patent_app_number] => 15/888307 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888307
Collision detection at multi-node storage sites Feb 4, 2018 Issued
Array ( [id] => 12571380 [patent_doc_number] => 10019379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Translation lookaside buffer switch bank [patent_app_type] => utility [patent_app_number] => 15/888961 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888961
Translation lookaside buffer switch bank Feb 4, 2018 Issued
Array ( [id] => 15544763 [patent_doc_number] => 10572161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Methods to configure and access scalable object stores using KV-SSDs and hybrid backend storage tiers of KV-SSDs, NVMe-SSDs and other flash devices [patent_app_type] => utility [patent_app_number] => 15/881706 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10959 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881706
Methods to configure and access scalable object stores using KV-SSDs and hybrid backend storage tiers of KV-SSDs, NVMe-SSDs and other flash devices Jan 25, 2018 Issued
Array ( [id] => 16844716 [patent_doc_number] => 11016802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Techniques for ordering atomic operations [patent_app_type] => utility [patent_app_number] => 15/881587 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10906 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881587
Techniques for ordering atomic operations Jan 25, 2018 Issued
Array ( [id] => 15700621 [patent_doc_number] => 10606486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Workload optimized planning, configuration, and monitoring for a storage system environment [patent_app_type] => utility [patent_app_number] => 15/881626 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11784 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881626
Workload optimized planning, configuration, and monitoring for a storage system environment Jan 25, 2018 Issued
Array ( [id] => 15547175 [patent_doc_number] => 10573377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Determining soft data for fractional digit memory cells [patent_app_type] => utility [patent_app_number] => 15/874529 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 15579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874529
Determining soft data for fractional digit memory cells Jan 17, 2018 Issued
Array ( [id] => 14539167 [patent_doc_number] => 20190205205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SEQUENTIAL MEMORY ACCESS ON A HIGH PERFORMANCE COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/861381 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861381 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/861381
Sequential memory access on a high performance computing system Jan 2, 2018 Issued
Array ( [id] => 13875523 [patent_doc_number] => 20190034102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => TECHNOLOGIES FOR DYNAMICALLY ALLOCATING DATA STORAGE CAPACITY FOR DIFFERENT DATA STORAGE TYPES [patent_app_type] => utility [patent_app_number] => 15/856220 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856220
Technologies for dynamically allocating data storage capacity for different data storage types Dec 27, 2017 Issued
Array ( [id] => 12848398 [patent_doc_number] => 20180174639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => ROW HAMMER REFRESH COMMAND [patent_app_type] => utility [patent_app_number] => 15/835050 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835050
Row hammer refresh command Dec 6, 2017 Issued
Array ( [id] => 15516565 [patent_doc_number] => 10564867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Validation of storage volumes that are in a peer to peer remote copy relationship [patent_app_type] => utility [patent_app_number] => 15/826360 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6882 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826360
Validation of storage volumes that are in a peer to peer remote copy relationship Nov 28, 2017 Issued
Array ( [id] => 14347537 [patent_doc_number] => 20190155741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => METHOD AND SYSTEM FOR LOW LATENCY DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/821374 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821374
Method and system for low latency data management Nov 21, 2017 Issued
Array ( [id] => 14249927 [patent_doc_number] => 10275163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Methods for controlling data transfer speed of a data storage device and a host device utilizing the same [patent_app_type] => utility [patent_app_number] => 15/820727 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5451 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820727
Methods for controlling data transfer speed of a data storage device and a host device utilizing the same Nov 21, 2017 Issued
Array ( [id] => 13830607 [patent_doc_number] => 20190018788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/820573 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820573
Memory system and method for controlling nonvolatile memory Nov 21, 2017 Issued
Array ( [id] => 14347573 [patent_doc_number] => 20190155759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => DUAL IN-LINE MEMORY MODULE WITH DEDICATED READ AND WRITE PORTS [patent_app_type] => utility [patent_app_number] => 15/820490 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820490
Dual in-line memory module with dedicated read and write ports Nov 21, 2017 Issued
Array ( [id] => 14735355 [patent_doc_number] => 10387077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Techniques for efficiently accessing values spanning slabs of memory [patent_app_type] => utility [patent_app_number] => 15/820407 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820407
Techniques for efficiently accessing values spanning slabs of memory Nov 20, 2017 Issued
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