Search

Kimberly E. Glenn

Examiner (ID: 1902, Phone: (571)272-1761 , Office: P/2842 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2843, 2842
Total Applications
1940
Issued Applications
1672
Pending Applications
121
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4942131 [patent_doc_number] => 20080079454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Apparatus for testing integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/698122 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2854 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20080079454.pdf [firstpage_image] =>[orig_patent_app_number] => 11698122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698122
Apparatus for testing integrated circuit Jan 25, 2007 Issued
Array ( [id] => 5190482 [patent_doc_number] => 20070168791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Circuit and method for testing embedded phase-locked loop circuit' [patent_app_type] => utility [patent_app_number] => 11/528017 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3700 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168791.pdf [firstpage_image] =>[orig_patent_app_number] => 11528017 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528017
Circuit and method for testing embedded phase-locked loop circuit Sep 26, 2006 Issued
Array ( [id] => 5243840 [patent_doc_number] => 20070022335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Methods and apparatus for interfacing between test system and memory' [patent_app_type] => utility [patent_app_number] => 11/517259 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6081 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022335.pdf [firstpage_image] =>[orig_patent_app_number] => 11517259 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517259
Methods and apparatus for interfacing between test system and memory Sep 7, 2006 Issued
Array ( [id] => 302151 [patent_doc_number] => 07539893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Systems and methods for speed binning of integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/513624 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8190 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539893.pdf [firstpage_image] =>[orig_patent_app_number] => 11513624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513624
Systems and methods for speed binning of integrated circuits Aug 30, 2006 Issued
Array ( [id] => 5129957 [patent_doc_number] => 20070206354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Slack-based transition-fault testing' [patent_app_type] => utility [patent_app_number] => 11/366679 [patent_app_country] => US [patent_app_date] => 2006-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20070206354.pdf [firstpage_image] =>[orig_patent_app_number] => 11366679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/366679
Slack-based transition-fault testing Mar 1, 2006 Issued
Array ( [id] => 5734538 [patent_doc_number] => 20060259655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Test method, test circuit, test circuit building-in device, and computer program' [patent_app_type] => utility [patent_app_number] => 11/359364 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3733 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259655.pdf [firstpage_image] =>[orig_patent_app_number] => 11359364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/359364
Test method, test circuit, test circuit building-in device, and computer program Feb 22, 2006 Abandoned
Array ( [id] => 340463 [patent_doc_number] => 07506228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Measuring the internal clock speed of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/353855 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5799 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506228.pdf [firstpage_image] =>[orig_patent_app_number] => 11353855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353855
Measuring the internal clock speed of an integrated circuit Feb 13, 2006 Issued
Array ( [id] => 5679492 [patent_doc_number] => 20060184848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Semiconductor integrated circuit having test function and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/335606 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8456 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184848.pdf [firstpage_image] =>[orig_patent_app_number] => 11335606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335606
Semiconductor integrated circuit having test function and manufacturing method Jan 19, 2006 Abandoned
Array ( [id] => 5868955 [patent_doc_number] => 20060163572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Semiconductor memory testing device and test method using the same' [patent_app_type] => utility [patent_app_number] => 11/336331 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6916 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163572.pdf [firstpage_image] =>[orig_patent_app_number] => 11336331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336331
Semiconductor memory testing device and test method using the same Jan 19, 2006 Issued
Array ( [id] => 5706695 [patent_doc_number] => 20060195743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/335464 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195743.pdf [firstpage_image] =>[orig_patent_app_number] => 11335464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335464
Semiconductor memory device Jan 19, 2006 Issued
Array ( [id] => 596851 [patent_doc_number] => 07454674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Digital jitter detector' [patent_app_type] => utility [patent_app_number] => 11/325123 [patent_app_country] => US [patent_app_date] => 2006-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5425 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454674.pdf [firstpage_image] =>[orig_patent_app_number] => 11325123 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325123
Digital jitter detector Jan 3, 2006 Issued
Array ( [id] => 366740 [patent_doc_number] => 07484155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Analog base-band test apparatus and method by enhanced combination of JTAG and memory in mobile communication system' [patent_app_type] => utility [patent_app_number] => 11/324707 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2729 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484155.pdf [firstpage_image] =>[orig_patent_app_number] => 11324707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324707
Analog base-band test apparatus and method by enhanced combination of JTAG and memory in mobile communication system Jan 2, 2006 Issued
Array ( [id] => 5255184 [patent_doc_number] => 20070136640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Defect detection and repair in an embedded random access memory' [patent_app_type] => utility [patent_app_number] => 11/300078 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136640.pdf [firstpage_image] =>[orig_patent_app_number] => 11300078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/300078
Defect detection and repair in an embedded random access memory Dec 13, 2005 Abandoned
Array ( [id] => 366738 [patent_doc_number] => 07484153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Systems and methods for LBIST testing using isolatable scan chains' [patent_app_type] => utility [patent_app_number] => 11/295057 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6633 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484153.pdf [firstpage_image] =>[orig_patent_app_number] => 11295057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295057
Systems and methods for LBIST testing using isolatable scan chains Dec 5, 2005 Issued
Array ( [id] => 4996199 [patent_doc_number] => 20070011544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Reprogramming of tester resource assignments' [patent_app_type] => utility [patent_app_number] => 11/153180 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5109 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011544.pdf [firstpage_image] =>[orig_patent_app_number] => 11153180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153180
Reprogramming of tester resource assignments Jun 14, 2005 Abandoned
Array ( [id] => 806216 [patent_doc_number] => 07424650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-09 [patent_title] => 'Circuit to measure skew' [patent_app_type] => utility [patent_app_number] => 11/152980 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424650.pdf [firstpage_image] =>[orig_patent_app_number] => 11152980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152980
Circuit to measure skew Jun 13, 2005 Issued
Array ( [id] => 372101 [patent_doc_number] => 07478294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Time controllable sensing scheme for sense amplifier in memory IC test' [patent_app_type] => utility [patent_app_number] => 11/152476 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2155 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478294.pdf [firstpage_image] =>[orig_patent_app_number] => 11152476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152476
Time controllable sensing scheme for sense amplifier in memory IC test Jun 13, 2005 Issued
Array ( [id] => 912451 [patent_doc_number] => 07334169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Generation of test mode signals in memory device with minimized wiring' [patent_app_type] => utility [patent_app_number] => 11/151053 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/334/07334169.pdf [firstpage_image] =>[orig_patent_app_number] => 11151053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151053
Generation of test mode signals in memory device with minimized wiring Jun 12, 2005 Issued
Array ( [id] => 379129 [patent_doc_number] => 07313741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Integrated semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/145192 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7649 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313741.pdf [firstpage_image] =>[orig_patent_app_number] => 11145192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145192
Integrated semiconductor memory Jun 5, 2005 Issued
Array ( [id] => 6979569 [patent_doc_number] => 20050289287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method and apparatus for interfacing between test system and embedded memory on test mode setting operation' [patent_app_type] => utility [patent_app_number] => 11/142673 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4364 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289287.pdf [firstpage_image] =>[orig_patent_app_number] => 11142673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/142673
Method and apparatus for interfacing between test system and embedded memory on test mode setting operation Jun 1, 2005 Abandoned
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