Search

Kimberly N. Mclean Mayo

Examiner (ID: 12031)

Most Active Art Unit
2187
Art Unit(s)
2185, 2187, 2751
Total Applications
382
Issued Applications
339
Pending Applications
11
Abandoned Applications
32

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 562251 [patent_doc_number] => 07165152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Method and apparatus for managing access to storage devices in a storage system with access control' [patent_app_type] => utility [patent_app_number] => 09/751684 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 29086 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165152.pdf [firstpage_image] =>[orig_patent_app_number] => 09751684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751684
Method and apparatus for managing access to storage devices in a storage system with access control Dec 28, 2000 Issued
Array ( [id] => 6134006 [patent_doc_number] => 20020078312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Support for single-node quorum in a two-node nodeset for a shared disk parallel file system' [patent_app_type] => new [patent_app_number] => 09/737393 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3882 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078312.pdf [firstpage_image] =>[orig_patent_app_number] => 09737393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737393
Support for single-node quorum in a two-node nodeset for a shared disk parallel file system Dec 14, 2000 Issued
Array ( [id] => 1027668 [patent_doc_number] => 06886082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Information processing system' [patent_app_type] => utility [patent_app_number] => 10/130629 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 82 [patent_no_of_words] => 18375 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886082.pdf [firstpage_image] =>[orig_patent_app_number] => 10130629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/130629
Information processing system Nov 20, 2000 Issued
Array ( [id] => 1452302 [patent_doc_number] => 06370624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Configurable page closing method and apparatus for multi-port host bridges' [patent_app_type] => B1 [patent_app_number] => 09/712010 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4887 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370624.pdf [firstpage_image] =>[orig_patent_app_number] => 09712010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712010
Configurable page closing method and apparatus for multi-port host bridges Nov 12, 2000 Issued
Array ( [id] => 7638607 [patent_doc_number] => 06397314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices' [patent_app_type] => B1 [patent_app_number] => 09/705474 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 13514 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397314.pdf [firstpage_image] =>[orig_patent_app_number] => 09705474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705474
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Nov 1, 2000 Issued
Array ( [id] => 1155029 [patent_doc_number] => 06779076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method and system for using dynamic random access memory as cache memory' [patent_app_type] => B1 [patent_app_number] => 09/684165 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4565 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779076.pdf [firstpage_image] =>[orig_patent_app_number] => 09684165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684165
Method and system for using dynamic random access memory as cache memory Oct 4, 2000 Issued
Array ( [id] => 1082988 [patent_doc_number] => 06836824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Method and apparatus for reducing power consumption in a cache memory system' [patent_app_type] => B1 [patent_app_number] => 09/670368 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 15258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836824.pdf [firstpage_image] =>[orig_patent_app_number] => 09670368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670368
Method and apparatus for reducing power consumption in a cache memory system Sep 25, 2000 Issued
Array ( [id] => 1587386 [patent_doc_number] => 06425051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'METHOD, SYSTEM, PROGRAM, AND DATA STRUCTURES FOR ENABLING A CONTROLLER ACCESSING A STORAGE DEVICE TO HANDLE REQUESTS TO DATA IN A FIRST DATA FORMAT WHEN THE STORAGE DEVICE INCLUDES DATA IN A SECOND DATA FORMAT' [patent_app_type] => B1 [patent_app_number] => 09/669782 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5413 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425051.pdf [firstpage_image] =>[orig_patent_app_number] => 09669782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669782
METHOD, SYSTEM, PROGRAM, AND DATA STRUCTURES FOR ENABLING A CONTROLLER ACCESSING A STORAGE DEVICE TO HANDLE REQUESTS TO DATA IN A FIRST DATA FORMAT WHEN THE STORAGE DEVICE INCLUDES DATA IN A SECOND DATA FORMAT Sep 24, 2000 Issued
Array ( [id] => 1271864 [patent_doc_number] => 06662278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Adaptive throttling of memory acceses, such as throttling RDRAM accesses in a real-time system' [patent_app_type] => B1 [patent_app_number] => 09/667649 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4500 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662278.pdf [firstpage_image] =>[orig_patent_app_number] => 09667649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667649
Adaptive throttling of memory acceses, such as throttling RDRAM accesses in a real-time system Sep 21, 2000 Issued
Array ( [id] => 7642387 [patent_doc_number] => 06430659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and means for increasing performance of multiprocessor computer systems by reducing accesses to global memory locations through the use of quanta' [patent_app_type] => B1 [patent_app_number] => 09/668503 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6327 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430659.pdf [firstpage_image] =>[orig_patent_app_number] => 09668503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668503
Method and means for increasing performance of multiprocessor computer systems by reducing accesses to global memory locations through the use of quanta Sep 21, 2000 Issued
Array ( [id] => 7633087 [patent_doc_number] => 06658533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method and apparatus for write cache flush and fill mechanisms' [patent_app_type] => B1 [patent_app_number] => 09/667405 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4186 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658533.pdf [firstpage_image] =>[orig_patent_app_number] => 09667405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667405
Method and apparatus for write cache flush and fill mechanisms Sep 20, 2000 Issued
Array ( [id] => 900097 [patent_doc_number] => 07343469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-11 [patent_title] => 'Remapping I/O device addresses into high memory using GART' [patent_app_type] => utility [patent_app_number] => 09/667050 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2588 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343469.pdf [firstpage_image] =>[orig_patent_app_number] => 09667050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667050
Remapping I/O device addresses into high memory using GART Sep 20, 2000 Issued
Array ( [id] => 1308941 [patent_doc_number] => 06629228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Proportionally growing stack in a linear memory array' [patent_app_type] => B1 [patent_app_number] => 09/666275 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4641 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629228.pdf [firstpage_image] =>[orig_patent_app_number] => 09666275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666275
Proportionally growing stack in a linear memory array Sep 20, 2000 Issued
Array ( [id] => 978750 [patent_doc_number] => 06934825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Bi-directional stack in a linear memory array' [patent_app_type] => utility [patent_app_number] => 09/671513 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 4429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934825.pdf [firstpage_image] =>[orig_patent_app_number] => 09671513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671513
Bi-directional stack in a linear memory array Sep 20, 2000 Issued
Array ( [id] => 1248855 [patent_doc_number] => 06678800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Cache apparatus and control method having writable modified state' [patent_app_type] => B1 [patent_app_number] => 09/667223 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 7871 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678800.pdf [firstpage_image] =>[orig_patent_app_number] => 09667223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667223
Cache apparatus and control method having writable modified state Sep 20, 2000 Issued
Array ( [id] => 1430343 [patent_doc_number] => 06526480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Cache apparatus and control method allowing speculative processing of data' [patent_app_type] => B1 [patent_app_number] => 09/646704 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 42 [patent_no_of_words] => 12829 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526480.pdf [firstpage_image] =>[orig_patent_app_number] => 09646704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/646704
Cache apparatus and control method allowing speculative processing of data Sep 20, 2000 Issued
Array ( [id] => 940436 [patent_doc_number] => 06973542 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Detecting when to prefetch inodes and then prefetching inodes in parallel' [patent_app_type] => utility [patent_app_number] => 09/618420 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3669 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973542.pdf [firstpage_image] =>[orig_patent_app_number] => 09618420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618420
Detecting when to prefetch inodes and then prefetching inodes in parallel Jul 17, 2000 Issued
Array ( [id] => 1595880 [patent_doc_number] => 06484237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Unified multilevel memory system architecture which supports both cache and addressable SRAM' [patent_app_type] => B1 [patent_app_number] => 09/603365 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 13077 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484237.pdf [firstpage_image] =>[orig_patent_app_number] => 09603365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603365
Unified multilevel memory system architecture which supports both cache and addressable SRAM Jun 25, 2000 Issued
Array ( [id] => 1580347 [patent_doc_number] => 06470428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Sequential memory access cache controller' [patent_app_type] => B1 [patent_app_number] => 09/529124 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2570 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470428.pdf [firstpage_image] =>[orig_patent_app_number] => 09529124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/529124
Sequential memory access cache controller Jun 25, 2000 Issued
Array ( [id] => 7638616 [patent_doc_number] => 06397305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and apparatus for controlling shared memory access' [patent_app_type] => B1 [patent_app_number] => 09/529367 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397305.pdf [firstpage_image] =>[orig_patent_app_number] => 09529367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/529367
Method and apparatus for controlling shared memory access Jun 25, 2000 Issued
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