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Kin Chan Chen

Examiner (ID: 8813)

Most Active Art Unit
1765
Art Unit(s)
1792, 1765
Total Applications
758
Issued Applications
583
Pending Applications
32
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20037979 [patent_doc_number] => 20250176201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT) [patent_app_type] => utility [patent_app_number] => 18/520527 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520527
SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT) Nov 26, 2023 Pending
Array ( [id] => 19255286 [patent_doc_number] => 20240206283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/389429 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389429
DISPLAY DEVICE Nov 13, 2023 Pending
Array ( [id] => 19308735 [patent_doc_number] => 20240237318 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => Configurable Faraday Cage [patent_app_type] => utility [patent_app_number] => 18/492687 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492687
Configurable Faraday Cage Oct 22, 2023 Pending
Array ( [id] => 19308735 [patent_doc_number] => 20240237318 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => Configurable Faraday Cage [patent_app_type] => utility [patent_app_number] => 18/492687 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492687
Configurable Faraday Cage Oct 21, 2023 Pending
Array ( [id] => 19206362 [patent_doc_number] => 20240178261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => CHIP PACKAGE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/491713 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491713
CHIP PACKAGE AND METHOD FOR FORMING THE SAME Oct 19, 2023 Pending
Array ( [id] => 19286038 [patent_doc_number] => 20240222516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 18/473976 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473976
THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME Sep 24, 2023 Pending
Array ( [id] => 19868414 [patent_doc_number] => 20250107200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MULTI-LAYER DIELECTRIC GATE SPACER FOR FIN FIELD EFFECT TRANSISTORS (FINFET) AND GATE-ALL-AROUND (GAA) DEVICES [patent_app_type] => utility [patent_app_number] => 18/473803 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473803
MULTI-LAYER DIELECTRIC GATE SPACER FOR FIN FIELD EFFECT TRANSISTORS (FINFET) AND GATE-ALL-AROUND (GAA) DEVICES Sep 24, 2023 Pending
Array ( [id] => 19850868 [patent_doc_number] => 20250096219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Inductive Heatable Particles in Semiconductor Module [patent_app_type] => utility [patent_app_number] => 18/368302 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368302
Inductive Heatable Particles in Semiconductor Module Sep 13, 2023 Pending
Array ( [id] => 19038200 [patent_doc_number] => 20240088015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS [patent_app_type] => utility [patent_app_number] => 18/462049 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462049
INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS Sep 5, 2023 Pending
Array ( [id] => 19696665 [patent_doc_number] => 20250015210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => INTEGRATED STRUCTURE OF WAVEGUIDE AND ACTIVE COMPONENT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/234788 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234788
INTEGRATED STRUCTURE OF WAVEGUIDE AND ACTIVE COMPONENT AND MANUFACTURING METHOD THEREOF Aug 15, 2023 Pending
Array ( [id] => 18975227 [patent_doc_number] => 20240055319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => CIRCUIT PACKAGE WITH IMPROVED THERMAL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/218670 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218670
CIRCUIT PACKAGE WITH IMPROVED THERMAL MANAGEMENT Jul 5, 2023 Pending
Array ( [id] => 19237419 [patent_doc_number] => 20240194614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SOLID STATE DRIVE APPARATUS AND DATA STORAGE APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/342182 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342182
SOLID STATE DRIVE APPARATUS AND DATA STORAGE APPARATUS INCLUDING THE SAME Jun 26, 2023 Pending
Array ( [id] => 19546420 [patent_doc_number] => 20240363456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => GAS-PERMEABLE PACKAGE LID OF CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/334396 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334396
GAS-PERMEABLE PACKAGE LID OF CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jun 13, 2023 Pending
Array ( [id] => 19191489 [patent_doc_number] => 20240170402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/205139 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205139
SEMICONDUCTOR DEVICE Jun 1, 2023 Pending
Array ( [id] => 19116421 [patent_doc_number] => 20240128171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/204241 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204241
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE May 30, 2023 Pending
Array ( [id] => 19252824 [patent_doc_number] => 20240203821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE HAVING TWO-PHASE COOLING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/202613 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202613
SEMICONDUCTOR DEVICE HAVING TWO-PHASE COOLING STRUCTURE May 25, 2023 Pending
Array ( [id] => 18774344 [patent_doc_number] => 20230369175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 18/144464 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144464
POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME May 7, 2023 Pending
Array ( [id] => 18757521 [patent_doc_number] => 20230360984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => Semiconductor Package Comprising Structures Configured to Withstand a Change of the Volume of a Potting Compound [patent_app_type] => utility [patent_app_number] => 18/142106 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142106
Semiconductor Package Comprising Structures Configured to Withstand a Change of the Volume of a Potting Compound May 1, 2023 Pending
Array ( [id] => 19546422 [patent_doc_number] => 20240363458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => CIRCUIT CHIPS INCORPORATING NEGATIVE POISSON`S RATIO STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/309408 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309408
CIRCUIT CHIPS INCORPORATING NEGATIVE POISSON`S RATIO STRUCTURES Apr 27, 2023 Pending
Array ( [id] => 18757465 [patent_doc_number] => 20230360927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/140375 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140375
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND SYSTEM Apr 26, 2023 Pending
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