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Kin Chan Chen

Examiner (ID: 4953)

Most Active Art Unit
1765
Art Unit(s)
1792, 1765
Total Applications
758
Issued Applications
583
Pending Applications
32
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 585401 [patent_doc_number] => 07442647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-28 [patent_title] => 'Structure and method for formation of cladded interconnects for MRAMs' [patent_app_type] => utility [patent_app_number] => 12/043129 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2050 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442647.pdf [firstpage_image] =>[orig_patent_app_number] => 12043129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043129
Structure and method for formation of cladded interconnects for MRAMs Mar 4, 2008 Issued
Array ( [id] => 4654940 [patent_doc_number] => 20080023800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Process for smoothening III-N substrates' [patent_app_type] => utility [patent_app_number] => 11/878713 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4547 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023800.pdf [firstpage_image] =>[orig_patent_app_number] => 11878713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878713
Process for smoothening III-N substrates Jul 25, 2007 Issued
Array ( [id] => 170468 [patent_doc_number] => 07662646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Plasma processing method and plasma processing apparatus for performing accurate end point detection' [patent_app_type] => utility [patent_app_number] => 11/687428 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 13759 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/662/07662646.pdf [firstpage_image] =>[orig_patent_app_number] => 11687428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687428
Plasma processing method and plasma processing apparatus for performing accurate end point detection Mar 15, 2007 Issued
Array ( [id] => 4698425 [patent_doc_number] => 20080220609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing' [patent_app_type] => utility [patent_app_number] => 11/683648 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2105 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220609.pdf [firstpage_image] =>[orig_patent_app_number] => 11683648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683648
Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing Mar 7, 2007 Issued
Array ( [id] => 5079813 [patent_doc_number] => 20070123037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method of forming pattern using fine pitch hard mask' [patent_app_type] => utility [patent_app_number] => 11/699476 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5197 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20070123037.pdf [firstpage_image] =>[orig_patent_app_number] => 11699476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699476
Method of forming pattern using fine pitch hard mask Jan 29, 2007 Issued
Array ( [id] => 4692834 [patent_doc_number] => 20080085605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'DRY ETCHING METHOD OF INSULATING FILM' [patent_app_type] => utility [patent_app_number] => 11/668057 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4978 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085605.pdf [firstpage_image] =>[orig_patent_app_number] => 11668057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668057
Dry etching method of insulating film Jan 28, 2007 Issued
Array ( [id] => 5159540 [patent_doc_number] => 20070172584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method of manufacturing patterned magnetic recording medium' [patent_app_type] => utility [patent_app_number] => 11/657720 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20070172584.pdf [firstpage_image] =>[orig_patent_app_number] => 11657720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657720
Method of manufacturing patterned magnetic recording medium Jan 24, 2007 Abandoned
Array ( [id] => 170609 [patent_doc_number] => 07662722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Air gap under on-chip passive device' [patent_app_type] => utility [patent_app_number] => 11/626548 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 6427 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/662/07662722.pdf [firstpage_image] =>[orig_patent_app_number] => 11626548 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626548
Air gap under on-chip passive device Jan 23, 2007 Issued
Array ( [id] => 4803159 [patent_doc_number] => 20080014747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'PROCESS FOR REMOVING HIGH STRESSED FILM USING LF OR HF BIAS POWER AND CAPACITIVELY COUPLED VHF SOURCE POWER WITH ENHANCED RESIDUE CAPTURE' [patent_app_type] => utility [patent_app_number] => 11/626151 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3802 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014747.pdf [firstpage_image] =>[orig_patent_app_number] => 11626151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626151
Process for removing high stressed film using LF or HF bias power and capacitively coupled VHF source power with enhanced residue capture Jan 22, 2007 Issued
Array ( [id] => 917100 [patent_doc_number] => 07323420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Method for manufacturing multi-thickness gate dielectric layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/652186 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323420.pdf [firstpage_image] =>[orig_patent_app_number] => 11652186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652186
Method for manufacturing multi-thickness gate dielectric layer of semiconductor device Jan 10, 2007 Issued
Array ( [id] => 4929055 [patent_doc_number] => 20080168418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation' [patent_app_type] => utility [patent_app_number] => 11/651253 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168418.pdf [firstpage_image] =>[orig_patent_app_number] => 11651253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651253
Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation Jan 7, 2007 Issued
Array ( [id] => 334261 [patent_doc_number] => 07507673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method for etching an object to be processed' [patent_app_type] => utility [patent_app_number] => 11/620501 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4832 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/507/07507673.pdf [firstpage_image] =>[orig_patent_app_number] => 11620501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620501
Method for etching an object to be processed Jan 4, 2007 Issued
Array ( [id] => 5023019 [patent_doc_number] => 20070148985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method of manufacturing trench structure for device' [patent_app_type] => utility [patent_app_number] => 11/648561 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6912 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148985.pdf [firstpage_image] =>[orig_patent_app_number] => 11648561 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648561
Method of manufacturing trench structure for device Jan 2, 2007 Abandoned
Array ( [id] => 5213320 [patent_doc_number] => 20070102400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'SYSTEMS AND METHODS FOR PROCESSING MICROFEATURE WORKPIECES' [patent_app_type] => utility [patent_app_number] => 11/619130 [patent_app_country] => US [patent_app_date] => 2007-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3633 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20070102400.pdf [firstpage_image] =>[orig_patent_app_number] => 11619130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619130
Systems and methods for processing microfeature workpieces Jan 1, 2007 Issued
Array ( [id] => 1076981 [patent_doc_number] => 07615494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method for fabricating semiconductor device including plug' [patent_app_type] => utility [patent_app_number] => 11/617688 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615494.pdf [firstpage_image] =>[orig_patent_app_number] => 11617688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/617688
Method for fabricating semiconductor device including plug Dec 27, 2006 Issued
Array ( [id] => 211489 [patent_doc_number] => 07622395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Two-step method for etching a fuse window on a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/616300 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622395.pdf [firstpage_image] =>[orig_patent_app_number] => 11616300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616300
Two-step method for etching a fuse window on a semiconductor substrate Dec 26, 2006 Issued
Array ( [id] => 267138 [patent_doc_number] => 07566663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Method for manufacturing semiconductor device or semiconductor wafer using a chucking unit' [patent_app_type] => utility [patent_app_number] => 11/641913 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8505 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566663.pdf [firstpage_image] =>[orig_patent_app_number] => 11641913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641913
Method for manufacturing semiconductor device or semiconductor wafer using a chucking unit Dec 19, 2006 Issued
Array ( [id] => 5191656 [patent_doc_number] => 20070080137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'METHOD OF CHARACTERIZING A CHAMBER BASED UPON CONCURRENT BEHAVIOR OF SELECTED PLASMA PARAMETERS AS A FUNCTION OF SOURCE POWER, BIAS POWER AND CHAMBER PRESSURE' [patent_app_type] => utility [patent_app_number] => 11/608944 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 19201 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080137.pdf [firstpage_image] =>[orig_patent_app_number] => 11608944 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608944
Method of characterizing a chamber based upon concurrent behavior of selected plasma parameters as a function of source power, bias power and chamber pressure Dec 10, 2006 Issued
Array ( [id] => 5085508 [patent_doc_number] => 20070275559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Method of manufacturing flash memory device' [patent_app_type] => utility [patent_app_number] => 11/605128 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1859 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275559.pdf [firstpage_image] =>[orig_patent_app_number] => 11605128 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605128
Method of manufacturing flash memory device Nov 27, 2006 Issued
Array ( [id] => 4896558 [patent_doc_number] => 20080116171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Method For The Preferential Polishing Of Silicon Nitride Versus Silicon Oxide' [patent_app_type] => utility [patent_app_number] => 11/562447 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2723 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116171.pdf [firstpage_image] =>[orig_patent_app_number] => 11562447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562447
Method For The Preferential Polishing Of Silicon Nitride Versus Silicon Oxide Nov 21, 2006 Abandoned
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