Kin Chan Chen

Array ( [id] => 1123469 [patent_doc_number] => 06794293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Trench etch process for low-k dielectrics' [patent_app_type] => B2 [patent_app_number] => 09/972765 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 29 [patent_no_of_words] => 4687 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794293.pdf [firstpage_image] =>[orig_patent_app_number] => 09972765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1168977 [patent_doc_number] => 06753260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Composite etching stop in semiconductor process integration' [patent_app_type] => B1 [patent_app_number] => 09/970787 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2165 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753260.pdf [firstpage_image] =>[orig_patent_app_number] => 09970787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6412633 [patent_doc_number] => 20020125213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Dry etching apparatus, etching method, and method of forming a wiring' [patent_app_type] => new [patent_app_number] => 09/966689 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11678 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125213.pdf [firstpage_image] =>[orig_patent_app_number] => 09966689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6290556 [patent_doc_number] => 20020055263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Oxide film etching method' [patent_app_type] => new [patent_app_number] => 09/956803 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8999 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055263.pdf [firstpage_image] =>[orig_patent_app_number] => 09956803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1096130 [patent_doc_number] => 06821898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of forming a multi-layer microfluidic device' [patent_app_type] => B2 [patent_app_number] => 09/952243 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 4547 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821898.pdf [firstpage_image] =>[orig_patent_app_number] => 09952243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1261540 [patent_doc_number] => 06664190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Pre STI-CMP planarization scheme' [patent_app_type] => B2 [patent_app_number] => 09/951916 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1453 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664190.pdf [firstpage_image] =>[orig_patent_app_number] => 09951916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1141654 [patent_doc_number] => 06777340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method of etching a silicon containing layer using multilayer masks' [patent_app_type] => B1 [patent_app_number] => 09/949505 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3295 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777340.pdf [firstpage_image] =>[orig_patent_app_number] => 09949505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1205724 [patent_doc_number] => 06716756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method for forming capacitor of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/942784 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716756.pdf [firstpage_image] =>[orig_patent_app_number] => 09942784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1346716 [patent_doc_number] => 06583061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method for creating an anti-blooming structure in a charge coupled device' [patent_app_type] => B2 [patent_app_number] => 09/944548 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1688 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583061.pdf [firstpage_image] =>[orig_patent_app_number] => 09944548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1235791 [patent_doc_number] => 06689696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method for manufacturing semiconductor device employing dielectric layer used to form conductive layer into three dimensional shape' [patent_app_type] => B2 [patent_app_number] => 09/939723 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6872 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689696.pdf [firstpage_image] =>[orig_patent_app_number] => 09939723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6137287 [patent_doc_number] => 20020000424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method and device for removing an unnecessary film' [patent_app_type] => new [patent_app_number] => 09/935569 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6354 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000424.pdf [firstpage_image] =>[orig_patent_app_number] => 09935569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6692753 [patent_doc_number] => 20030040185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Process for device using partial SOI' [patent_app_type] => new [patent_app_number] => 09/938042 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2943 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040185.pdf [firstpage_image] =>[orig_patent_app_number] => 09938042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1165644 [patent_doc_number] => 06756312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method of fabricating a semiconductor device including time-selective etching process' [patent_app_type] => B2 [patent_app_number] => 09/934453 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 9991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756312.pdf [firstpage_image] =>[orig_patent_app_number] => 09934453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6836988 [patent_doc_number] => 20030034328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'METHOD OF MAKING 3D PATTERNS ON A MOLD' [patent_app_type] => new [patent_app_number] => 09/933212 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1393 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034328.pdf [firstpage_image] =>[orig_patent_app_number] => 09933212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6838936 [patent_doc_number] => 20030036276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method for forming high resistance resistor with integrated high voltage device process' [patent_app_type] => new [patent_app_number] => 09/931953 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1805 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036276.pdf [firstpage_image] =>[orig_patent_app_number] => 09931953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7625516 [patent_doc_number] => 06723653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material' [patent_app_type] => B1 [patent_app_number] => 09/932527 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3179 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723653.pdf [firstpage_image] =>[orig_patent_app_number] => 09932527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6838941 [patent_doc_number] => 20030036281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method of substrate processing and photoresist exposure' [patent_app_type] => new [patent_app_number] => 09/930840 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2893 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036281.pdf [firstpage_image] =>[orig_patent_app_number] => 09930840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134530 [patent_doc_number] => 06784109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method for fabricating semiconductor devices including wiring forming with a porous low-k film and copper' [patent_app_type] => B2 [patent_app_number] => 09/920834 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5612 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784109.pdf [firstpage_image] =>[orig_patent_app_number] => 09920834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6617831 [patent_doc_number] => 20020016078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Method for etching silicon oxynitride and dielectric antireflection coatings' [patent_app_type] => new [patent_app_number] => 09/920251 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8831 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016078.pdf [firstpage_image] =>[orig_patent_app_number] => 09920251 [rel_patent_id] =>[rel_patent_doc_number] =>)