Kin Chan Chen

Array ( [id] => 4351271 [patent_doc_number] => 06291358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Plasma deposition tool operating method' [patent_app_type] => 1 [patent_app_number] => 9/419400 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2489 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291358.pdf [firstpage_image] =>[orig_patent_app_number] => 419400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294377 [patent_doc_number] => 06197695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Process for the manufacture of passive and active components on the same insulating substrate' [patent_app_type] => 1 [patent_app_number] => 9/419303 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3899 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197695.pdf [firstpage_image] =>[orig_patent_app_number] => 419303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4355190 [patent_doc_number] => 06200900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method for formation of an air gap in an integrated circuit architecture' [patent_app_type] => 1 [patent_app_number] => 9/415315 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3316 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200900.pdf [firstpage_image] =>[orig_patent_app_number] => 415315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344973 [patent_doc_number] => 06284662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of forming a cobalt silicide layer by use of a TEOS through oxide film for ion-implantation process' [patent_app_type] => 1 [patent_app_number] => 9/406715 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12967 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284662.pdf [firstpage_image] =>[orig_patent_app_number] => 406715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156493 [patent_doc_number] => 06156661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Post clean treatment' [patent_app_type] => 1 [patent_app_number] => 9/384946 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6700 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156661.pdf [firstpage_image] =>[orig_patent_app_number] => 384946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1205728 [patent_doc_number] => 06716758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Aspect ratio controlled etch selectivity using time modulated DC bias voltage' [patent_app_type] => B1 [patent_app_number] => 09/382584 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4581 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716758.pdf [firstpage_image] =>[orig_patent_app_number] => 09382584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4178380 [patent_doc_number] => 06037264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method for removing redeposited veils from etched platinum' [patent_app_type] => 1 [patent_app_number] => 9/371593 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 13516 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037264.pdf [firstpage_image] =>[orig_patent_app_number] => 371593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215898 [patent_doc_number] => 06087265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for removing redeposited veils from etched platinum' [patent_app_type] => 1 [patent_app_number] => 9/371610 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 13518 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087265.pdf [firstpage_image] =>[orig_patent_app_number] => 371610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408904 [patent_doc_number] => 06300250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method of forming bumps for flip chip applications' [patent_app_type] => 1 [patent_app_number] => 9/369260 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300250.pdf [firstpage_image] =>[orig_patent_app_number] => 369260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247766 [patent_doc_number] => 06221778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/368166 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1492 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221778.pdf [firstpage_image] =>[orig_patent_app_number] => 368166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4276194 [patent_doc_number] => 06281135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Oxygen free plasma stripping process' [patent_app_type] => 1 [patent_app_number] => 9/368553 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6531 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281135.pdf [firstpage_image] =>[orig_patent_app_number] => 368553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446671 [patent_doc_number] => 06368974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching' [patent_app_type] => B1 [patent_app_number] => 09/365416 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2971 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368974.pdf [firstpage_image] =>[orig_patent_app_number] => 09365416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259251 [patent_doc_number] => 06204186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method of making integrated circuit capacitor including tapered plug' [patent_app_type] => 1 [patent_app_number] => 9/364366 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3050 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204186.pdf [firstpage_image] =>[orig_patent_app_number] => 364366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1490371 [patent_doc_number] => 06417112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Post etch cleaning composition and process for dual damascene system' [patent_app_type] => B1 [patent_app_number] => 09/343532 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 42 [patent_no_of_words] => 7790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417112.pdf [firstpage_image] =>[orig_patent_app_number] => 09343532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6972926 [patent_doc_number] => 20010003268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'PROCESS FOR PREPARING DEFFECT FREE SILICON CRYSTALS WHICH ALLOWS FOR VARIABILITY IN PROCESS CONITIONS' [patent_app_type] => new-utility [patent_app_number] => 09/344036 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13308 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003268.pdf [firstpage_image] =>[orig_patent_app_number] => 09344036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7093258 [patent_doc_number] => 20010034136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'METHOD FOR IMPROVING CONTACT RESISTANCE OF SILICIDE LAYER IN A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/336712 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034136.pdf [firstpage_image] =>[orig_patent_app_number] => 09336712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6973610 [patent_doc_number] => 20010003672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'POLISHING COMPOSITION AND SURFACE TREATING COMPOSITION' [patent_app_type] => new-utility [patent_app_number] => 09/336680 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5928 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003672.pdf [firstpage_image] =>[orig_patent_app_number] => 09336680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4351240 [patent_doc_number] => 06291356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for etching silicon oxynitride and dielectric antireflection coatings' [patent_app_type] => 1 [patent_app_number] => 9/317655 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8945 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291356.pdf [firstpage_image] =>[orig_patent_app_number] => 317655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095323 [patent_doc_number] => 06096650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Treatment of a surface having exposed silica' [patent_app_type] => 1 [patent_app_number] => 9/314870 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2433 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096650.pdf [firstpage_image] =>[orig_patent_app_number] => 314870 [rel_patent_id] =>[rel_patent_doc_number] =>)