
King Y. Poon
Supervisory Patent Examiner (ID: 10953, Phone: (571)272-7440 , Office: P/2675 )
| Most Active Art Unit | 2624 |
| Art Unit(s) | 2625, 2675, 2624, 2617, 2724 |
| Total Applications | 269 |
| Issued Applications | 173 |
| Pending Applications | 47 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4163348
[patent_doc_number] => 06114748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'AC plasma display panel provided with glaze layer having conductive member'
[patent_app_type] => 1
[patent_app_number] => 9/100944
[patent_app_country] => US
[patent_app_date] => 1998-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5244
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114748.pdf
[firstpage_image] =>[orig_patent_app_number] => 100944
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100944 | AC plasma display panel provided with glaze layer having conductive member | Jun 21, 1998 | Issued |
Array
(
[id] => 4055986
[patent_doc_number] => 05969387
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Lateral thin-film SOI devices with graded top oxide and graded drift region'
[patent_app_type] => 1
[patent_app_number] => 9/100832
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2699
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969387.pdf
[firstpage_image] =>[orig_patent_app_number] => 100832
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100832 | Lateral thin-film SOI devices with graded top oxide and graded drift region | Jun 18, 1998 | Issued |
Array
(
[id] => 4184962
[patent_doc_number] => RE036837
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Structure of contact between wiring layers in semiconductor integrated circuit device'
[patent_app_type] => 2
[patent_app_number] => 9/100009
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_no_of_words] => 5900
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036837.pdf
[firstpage_image] =>[orig_patent_app_number] => 100009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100009 | Structure of contact between wiring layers in semiconductor integrated circuit device | Jun 18, 1998 | Issued |
Array
(
[id] => 4212579
[patent_doc_number] => 06028355
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Method and apparatus for dissipating heat from an enclosed printed wiring board'
[patent_app_type] => 1
[patent_app_number] => 9/097971
[patent_app_country] => US
[patent_app_date] => 1998-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2262
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[pdf_file] => patents/06/028/06028355.pdf
[firstpage_image] =>[orig_patent_app_number] => 097971
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/097971 | Method and apparatus for dissipating heat from an enclosed printed wiring board | Jun 15, 1998 | Issued |
Array
(
[id] => 3926998
[patent_doc_number] => 05914525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/094911
[patent_app_country] => US
[patent_app_date] => 1998-06-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/914/05914525.pdf
[firstpage_image] =>[orig_patent_app_number] => 094911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094911 | Semiconductor device | Jun 11, 1998 | Issued |
Array
(
[id] => 4422524
[patent_doc_number] => 06194758
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Semiconductor device comprising capacitor and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/095612
[patent_app_country] => US
[patent_app_date] => 1998-06-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/194/06194758.pdf
[firstpage_image] =>[orig_patent_app_number] => 095612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095612 | Semiconductor device comprising capacitor and method of fabricating the same | Jun 10, 1998 | Issued |
Array
(
[id] => 4123472
[patent_doc_number] => 06072217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Tunable threshold SOI device using isolated well structure for back gate'
[patent_app_type] => 1
[patent_app_number] => 9/095551
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[patent_app_date] => 1998-06-11
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[pdf_file] => patents/06/072/06072217.pdf
[firstpage_image] =>[orig_patent_app_number] => 095551
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095551 | Tunable threshold SOI device using isolated well structure for back gate | Jun 10, 1998 | Issued |
Array
(
[id] => 4222642
[patent_doc_number] => 06087692
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'DRAM cell configuration and method for its fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/093572
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 8169
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[pdf_file] => patents/06/087/06087692.pdf
[firstpage_image] =>[orig_patent_app_number] => 093572
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093572 | DRAM cell configuration and method for its fabrication | Jun 7, 1998 | Issued |
Array
(
[id] => 4239245
[patent_doc_number] => 06118160
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Structure of a mask ROM device on a semiconductor substrate having a cell area for coding'
[patent_app_type] => 1
[patent_app_number] => 9/088457
[patent_app_country] => US
[patent_app_date] => 1998-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/118/06118160.pdf
[firstpage_image] =>[orig_patent_app_number] => 088457
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088457 | Structure of a mask ROM device on a semiconductor substrate having a cell area for coding | May 31, 1998 | Issued |
Array
(
[id] => 4180249
[patent_doc_number] => 06084306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Bridging method of interconnects for integrated circuit packages'
[patent_app_type] => 1
[patent_app_number] => 9/087440
[patent_app_country] => US
[patent_app_date] => 1998-05-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/084/06084306.pdf
[firstpage_image] =>[orig_patent_app_number] => 087440
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/087440 | Bridging method of interconnects for integrated circuit packages | May 28, 1998 | Issued |
Array
(
[id] => 4026852
[patent_doc_number] => 05925902
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Semiconductor device having a schottky film with a vertical gap formed therein'
[patent_app_type] => 1
[patent_app_number] => 9/086723
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[pdf_file] => patents/05/925/05925902.pdf
[firstpage_image] =>[orig_patent_app_number] => 086723
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086723 | Semiconductor device having a schottky film with a vertical gap formed therein | May 28, 1998 | Issued |
Array
(
[id] => 4056607
[patent_doc_number] => 05969428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Alignment mark, manufacturing method thereof, exposing method using the alignment mark, semiconductor device manufactured using the exposing method'
[patent_app_type] => 1
[patent_app_number] => 9/086609
[patent_app_country] => US
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[pdf_file] => patents/05/969/05969428.pdf
[firstpage_image] =>[orig_patent_app_number] => 086609
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086609 | Alignment mark, manufacturing method thereof, exposing method using the alignment mark, semiconductor device manufactured using the exposing method | May 28, 1998 | Issued |
Array
(
[id] => 4189200
[patent_doc_number] => 06150682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Photoelectric conversion device and image sensor'
[patent_app_type] => 1
[patent_app_number] => 9/085083
[patent_app_country] => US
[patent_app_date] => 1998-05-26
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[pdf_file] => patents/06/150/06150682.pdf
[firstpage_image] =>[orig_patent_app_number] => 085083
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/085083 | Photoelectric conversion device and image sensor | May 25, 1998 | Issued |
Array
(
[id] => 4423568
[patent_doc_number] => 06177699
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[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation'
[patent_app_type] => 1
[patent_app_number] => 9/083373
[patent_app_country] => US
[patent_app_date] => 1998-05-21
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[pdf_file] => patents/06/177/06177699.pdf
[firstpage_image] =>[orig_patent_app_number] => 083373
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083373 | DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation | May 20, 1998 | Issued |
Array
(
[id] => 4136726
[patent_doc_number] => 06034384
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays'
[patent_app_type] => 1
[patent_app_number] => 9/081653
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[firstpage_image] =>[orig_patent_app_number] => 081653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/081653 | Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays | May 19, 1998 | Issued |
Array
(
[id] => 3944445
[patent_doc_number] => 05973379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Ferroelectric semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/080480
[patent_app_country] => US
[patent_app_date] => 1998-05-18
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[firstpage_image] =>[orig_patent_app_number] => 080480
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080480 | Ferroelectric semiconductor device | May 17, 1998 | Issued |
Array
(
[id] => 3926814
[patent_doc_number] => 05914513
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Electronically tunable capacitor'
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[patent_app_number] => 9/081389
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[firstpage_image] =>[orig_patent_app_number] => 081389
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/081389 | Electronically tunable capacitor | May 17, 1998 | Issued |
Array
(
[id] => 4224488
[patent_doc_number] => 06040595
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080131 | Structure of a non-destructive readout dynamic random access memory | May 14, 1998 | Issued |
Array
(
[id] => 4362749
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[pdf_file] => patents/06/175/06175147.pdf
[firstpage_image] =>[orig_patent_app_number] => 079212
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/079212 | Device isolation for semiconductor devices | May 13, 1998 | Issued |
Array
(
[id] => 4057376
[patent_doc_number] => 05932916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Electrostatic discharge protection circuit'
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[patent_app_number] => 9/078134
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/932/05932916.pdf
[firstpage_image] =>[orig_patent_app_number] => 078134
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/078134 | Electrostatic discharge protection circuit | May 13, 1998 | Issued |