Search

Kirsten Sachwitz Apple

Examiner (ID: 9129, Phone: (571)272-5588 , Office: P/3694 )

Most Active Art Unit
3694
Art Unit(s)
3693, 3694, 3691, 3698, 3628, 3697
Total Applications
719
Issued Applications
408
Pending Applications
55
Abandoned Applications
275

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20450209 [patent_doc_number] => 20260006938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => CIGS SOLAR CELL WITH BOTH TRANSPARENCY AND FLEXIBILITY AND ITS MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/984274 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984274
CIGS SOLAR CELL WITH BOTH TRANSPARENCY AND FLEXIBILITY AND ITS MANUFACTURING METHOD Dec 16, 2024 Pending
Array ( [id] => 19436202 [patent_doc_number] => 20240304700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => DEEP TRENCH CAPACITOR INCLUDING A COMPACT CONTACT REGION AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/662146 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662146
DEEP TRENCH CAPACITOR INCLUDING A COMPACT CONTACT REGION AND METHODS OF FORMING THE SAME May 12, 2024 Pending
Array ( [id] => 19305244 [patent_doc_number] => 20240233824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 18/614908 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614908
Integrated circuit devices including arc protection diodes for memory structures Mar 24, 2024 Issued
Array ( [id] => 20252907 [patent_doc_number] => 20250301776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TRANSISTOR INTEGRATION FOR REDUCED LATERAL SPACE AND IMPROVED BREAKDOWN VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/615446 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615446
TRANSISTOR INTEGRATION FOR REDUCED LATERAL SPACE AND IMPROVED BREAKDOWN VOLTAGE Mar 24, 2024 Pending
Array ( [id] => 20167879 [patent_doc_number] => 20250259926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => HYBRID BOND FEATURES IN PROGRAMMABLE CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/440926 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440926
HYBRID BOND FEATURES IN PROGRAMMABLE CIRCUITS Feb 12, 2024 Pending
Array ( [id] => 19436106 [patent_doc_number] => 20240304604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/440801 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440801
DISPLAY DEVICE Feb 12, 2024 Pending
Array ( [id] => 20141043 [patent_doc_number] => 20250248087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/435511 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435511
INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME Feb 6, 2024 Pending
Array ( [id] => 19788605 [patent_doc_number] => 20250062284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => THIN WAFER, METHOD OF MANUFACTURING THE THIN WAFER, STACK TYPE SEMICONDUCTOR DEVICE INCLUDING THE THIN WAFER AND METHOD OF MANUFACTURING THE STACK TYPE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/434610 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434610
THIN WAFER, METHOD OF MANUFACTURING THE THIN WAFER, STACK TYPE SEMICONDUCTOR DEVICE INCLUDING THE THIN WAFER AND METHOD OF MANUFACTURING THE STACK TYPE SEMICONDUCTOR DEVICE Feb 5, 2024 Pending
Array ( [id] => 19714545 [patent_doc_number] => 20250024687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => 3-DIMENSIONAL (3D) FERROELECTRIC RANDOM ACCESS MEMORY (FeRAM) AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/422660 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422660
3-DIMENSIONAL (3D) FERROELECTRIC RANDOM ACCESS MEMORY (FeRAM) AND METHOD OF MANUFACTURING THE SAME Jan 24, 2024 Pending
Array ( [id] => 19335787 [patent_doc_number] => 20240250217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Plug Regrowth for Micro LED Uniformity and Efficiency Improvement [patent_app_type] => utility [patent_app_number] => 18/408137 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408137
Plug Regrowth for Micro LED Uniformity and Efficiency Improvement Jan 8, 2024 Pending
Array ( [id] => 19288079 [patent_doc_number] => 20240224562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ELECTROLUMINESCENT DEVICE, PRODUCTION METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/400128 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400128
ELECTROLUMINESCENT DEVICE, PRODUCTION METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME Dec 28, 2023 Pending
Array ( [id] => 19621487 [patent_doc_number] => 20240407167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/491603 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491603
THREE-DIMENSIONAL MEMORY DEVICE AND FORMATION METHOD THEREOF Oct 19, 2023 Pending
Array ( [id] => 19130872 [patent_doc_number] => 20240136225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY [patent_app_type] => utility [patent_app_number] => 18/486370 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486370 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486370
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY Oct 12, 2023 Pending
Array ( [id] => 19130872 [patent_doc_number] => 20240136225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY [patent_app_type] => utility [patent_app_number] => 18/486370 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486370 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486370
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY Oct 11, 2023 Pending
Array ( [id] => 18929295 [patent_doc_number] => 20240032299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => THREE-DIMENSIONAL MEMORY ARRAY WITH DUAL-LEVEL PERIPHERAL CIRCUITS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/480855 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18480855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/480855
THREE-DIMENSIONAL MEMORY ARRAY WITH DUAL-LEVEL PERIPHERAL CIRCUITS AND METHODS FOR FORMING THE SAME Oct 3, 2023 Pending
Array ( [id] => 19804052 [patent_doc_number] => 20250069977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => PHOTONICS CHIP PACKAGE STRUCTURES INCLUDING A CONTROLLED UNDERFILL FILLET [patent_app_type] => utility [patent_app_number] => 18/236985 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236985
PHOTONICS CHIP PACKAGE STRUCTURES INCLUDING A CONTROLLED UNDERFILL FILLET Aug 22, 2023 Pending
Array ( [id] => 19146434 [patent_doc_number] => 20240145464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/453965 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453965 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453965
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME Aug 21, 2023 Pending
Array ( [id] => 18945639 [patent_doc_number] => 20240040778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => MEMORY STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/451565 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451565 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451565
MEMORY STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Aug 16, 2023 Pending
Array ( [id] => 19271533 [patent_doc_number] => 20240215240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => NAND PLANE BOUNDARY SHRINK [patent_app_type] => utility [patent_app_number] => 18/358584 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358584
NAND PLANE BOUNDARY SHRINK Jul 24, 2023 Pending
Array ( [id] => 19351302 [patent_doc_number] => 20240260266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINERS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/356896 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356896
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINERS AND METHODS OF FORMING THE SAME Jul 20, 2023 Pending
Menu