Koosha Sharifi-tafreshi

Array ( [id] => 10377878 [patent_doc_number] => 20150262885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR-ON-INSULATOR (SOI) BODY CONTACTS AND METHODS FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/213288 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10377905 [patent_doc_number] => 20150262912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Via Corner Engineering in Trench-First Dual Damascene Process' [patent_app_type] => utility [patent_app_number] => 14/213329 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4231 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14213329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10378161 [patent_doc_number] => 20150263168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Structure and Method for Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/208294 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10377869 [patent_doc_number] => 20150262876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/208157 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6428 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10525506 [patent_doc_number] => 09252026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Buried trench isolation in integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/207303 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14207303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9667959 [patent_doc_number] => 20140231822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'VERTICAL TOPOLOGY LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/179488 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9515183 [patent_doc_number] => 20140151675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/174494 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9503422 [patent_doc_number] => 08741735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method of forming a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/173552 [patent_app_country] => US [patent_app_date] => 2014-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9490047 [patent_doc_number] => 20140140453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'STACKED DIGITAL/RF SYSTEM-ON-CHIP WITH INTEGRAL ISOLATION LAYER' [patent_app_type] => utility [patent_app_number] => 14/164352 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2372 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9488388 [patent_doc_number] => 20140138795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS' [patent_app_type] => utility [patent_app_number] => 14/165121 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4728 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9460465 [patent_doc_number] => 20140124891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'FUSE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/151862 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9463472 [patent_doc_number] => 20140127899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/152127 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7344 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9449528 [patent_doc_number] => 20140120698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH' [patent_app_type] => utility [patent_app_number] => 14/148499 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10082 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11432353 [patent_doc_number] => 09570680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method for fabricating electronic devices having semiconductor memory unit' [patent_app_type] => utility [patent_app_number] => 14/145782 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 81 [patent_no_of_words] => 20252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9603138 [patent_doc_number] => 20140199820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/143255 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9839104 [patent_doc_number] => 20150031185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED THEREBY' [patent_app_type] => utility [patent_app_number] => 14/139502 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 10091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9656851 [patent_doc_number] => 20140227856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICE HAVING SHALLOW TRENCH ISOLATION (STI)' [patent_app_type] => utility [patent_app_number] => 14/138552 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10464046 [patent_doc_number] => 20150349061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHODS FOR FABRICATING GRAPHENE DEVICE TOPOGRAPHY AND DEVICES FORMED THEREFROM' [patent_app_type] => utility [patent_app_number] => 14/654776 [patent_app_country] => US [patent_app_date] => 2013-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 22199 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14654776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9569307 [patent_doc_number] => 20140187020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD FOR LOW TEMPERATURE LAYER TRANSFER IN THE PREPARATION OF MULTILAYER SEMICONDUTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/133893 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4447 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9613554 [patent_doc_number] => 20140203411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/134325 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5017 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134325 [rel_patent_id] =>[rel_patent_doc_number] =>)