Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 9046761
[patent_doc_number] => 08541315
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-24
[patent_title] => 'High throughput epitaxial lift off for flexible electronics'
[patent_app_type] => utility
[patent_app_number] => 13/236119
[patent_app_country] => US
[patent_app_date] => 2011-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 6130
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236119
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/236119 | High throughput epitaxial lift off for flexible electronics | Sep 18, 2011 | Issued |
Array
(
[id] => 10502531
[patent_doc_number] => 09230933
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-05
[patent_title] => 'Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure'
[patent_app_type] => utility
[patent_app_number] => 13/234366
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 50
[patent_no_of_words] => 9541
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234366
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/234366 | Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure | Sep 15, 2011 | Issued |
Array
(
[id] => 8720795
[patent_doc_number] => 20130072012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'Method For Forming Package Substrate With Ultra-Thin Seed Layer'
[patent_app_type] => utility
[patent_app_number] => 13/235347
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2977
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235347
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/235347 | Method For Forming Package Substrate With Ultra-Thin Seed Layer | Sep 15, 2011 | Abandoned |
Array
(
[id] => 17166188
[patent_doc_number] => 11152300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Electrical fuse with metal line migration
[patent_app_type] => utility
[patent_app_number] => 13/234205
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 25
[patent_no_of_words] => 5945
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234205
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/234205 | Electrical fuse with metal line migration | Sep 15, 2011 | Issued |
Array
(
[id] => 8720778
[patent_doc_number] => 20130071995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'Method of Manufacturing a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 13/234296
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5056
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234296
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/234296 | Method of manufacturing a semiconductor device | Sep 15, 2011 | Issued |
Array
(
[id] => 8720802
[patent_doc_number] => 20130072019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'METHODS FOR FORMING SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/235194
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2836
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235194
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/235194 | Methods for forming semiconductor devices | Sep 15, 2011 | Issued |
Array
(
[id] => 10525503
[patent_doc_number] => 09252023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Etching method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/234975
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3208
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234975
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/234975 | Etching method and apparatus | Sep 15, 2011 | Issued |
Array
(
[id] => 9127092
[patent_doc_number] => 08575041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Repair of damaged surface areas of sensitive low-K dielectrics of microstructure devices after plasma processing by in situ treatment'
[patent_app_type] => utility
[patent_app_number] => 13/233590
[patent_app_country] => US
[patent_app_date] => 2011-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 7612
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13233590
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/233590 | Repair of damaged surface areas of sensitive low-K dielectrics of microstructure devices after plasma processing by in situ treatment | Sep 14, 2011 | Issued |
Array
(
[id] => 8705480
[patent_doc_number] => 20130062769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-14
[patent_title] => 'Microstructure Modification in Copper Interconnect Structures'
[patent_app_type] => utility
[patent_app_number] => 13/232085
[patent_app_country] => US
[patent_app_date] => 2011-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7279
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232085
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/232085 | Microstructure modification in copper interconnect structures | Sep 13, 2011 | Issued |
Array
(
[id] => 8928052
[patent_doc_number] => 20130183812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'METHOD FOR MANUFACTURING ELECTRONIC PARTS'
[patent_app_type] => utility
[patent_app_number] => 13/825673
[patent_app_country] => US
[patent_app_date] => 2011-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5804
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825673
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/825673 | Method for manufacturing electronic parts | Sep 13, 2011 | Issued |
Array
(
[id] => 8928047
[patent_doc_number] => 20130183807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS AND ELECTRONIC EQUIPMENT'
[patent_app_type] => utility
[patent_app_number] => 13/824206
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9139
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13824206
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/824206 | Method of manufacturing a semiconductor apparatus and electronic equipment | Sep 8, 2011 | Issued |
Array
(
[id] => 7662877
[patent_doc_number] => 20110312146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-22
[patent_title] => 'BIPOLAR DEVICE HAVING BURIED CONTACTS'
[patent_app_type] => utility
[patent_app_number] => 13/222877
[patent_app_country] => US
[patent_app_date] => 2011-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3508
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0312/20110312146.pdf
[firstpage_image] =>[orig_patent_app_number] => 13222877
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/222877 | Bipolar device having buried contacts | Aug 30, 2011 | Issued |
Array
(
[id] => 8586306
[patent_doc_number] => 20130005127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'METHOD FOR MANUFACTURING MULTIGATE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/322473
[patent_app_country] => US
[patent_app_date] => 2011-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3424
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13322473
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/322473 | Method for manufacturing multigate device | Jul 26, 2011 | Issued |
Array
(
[id] => 8630520
[patent_doc_number] => 08362593
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-29
[patent_title] => 'Method for stacking semiconductor dies'
[patent_app_type] => utility
[patent_app_number] => 13/168351
[patent_app_country] => US
[patent_app_date] => 2011-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168351
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/168351 | Method for stacking semiconductor dies | Jun 23, 2011 | Issued |
Array
(
[id] => 7654620
[patent_doc_number] => 20110303889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-15
[patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/166362
[patent_app_country] => US
[patent_app_date] => 2011-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3878
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0303/20110303889.pdf
[firstpage_image] =>[orig_patent_app_number] => 13166362
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/166362 | Variable resistance memory device having reduced bottom contact area and method of forming the same | Jun 21, 2011 | Issued |
Array
(
[id] => 9603141
[patent_doc_number] => 20140199823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/110690
[patent_app_country] => US
[patent_app_date] => 2011-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2183
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14110690
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/110690 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Jun 9, 2011 | Abandoned |
Array
(
[id] => 7564924
[patent_doc_number] => 20110284987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-24
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/110630
[patent_app_country] => US
[patent_app_date] => 2011-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7036
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0284/20110284987.pdf
[firstpage_image] =>[orig_patent_app_number] => 13110630
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/110630 | Semiconductor device | May 17, 2011 | Issued |
Array
(
[id] => 8205222
[patent_doc_number] => 20120126368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'Semiconductor Package'
[patent_app_type] => utility
[patent_app_number] => 13/109740
[patent_app_country] => US
[patent_app_date] => 2011-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3127
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20120126368.pdf
[firstpage_image] =>[orig_patent_app_number] => 13109740
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/109740 | Semiconductor package | May 16, 2011 | Issued |
Array
(
[id] => 8333235
[patent_doc_number] => 20120199938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'Semiconductor Memory Device and Method of Manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/108501
[patent_app_country] => US
[patent_app_date] => 2011-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6620
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13108501
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/108501 | Semiconductor memory device and method of manufacturing the same | May 15, 2011 | Issued |
Array
(
[id] => 9312400
[patent_doc_number] => 08653623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'One-time programmable devices and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 13/107409
[patent_app_country] => US
[patent_app_date] => 2011-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3800
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13107409
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/107409 | One-time programmable devices and methods of forming the same | May 12, 2011 | Issued |