Koosha Sharifi-tafreshi

Array ( [id] => 4887038 [patent_doc_number] => 20080261370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/155272 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6624 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20080261370.pdf [firstpage_image] =>[orig_patent_app_number] => 12155272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4695487 [patent_doc_number] => 20080217671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHODS FOR FORMING SEMICONDUCTOR STRUCTURES WITH BURIED ISOLATION COLLARS AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS' [patent_app_type] => utility [patent_app_number] => 12/125326 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8296 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217671.pdf [firstpage_image] =>[orig_patent_app_number] => 12125326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4719523 [patent_doc_number] => 20080242046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method on Forming an Isolation Film or a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/112679 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242046.pdf [firstpage_image] =>[orig_patent_app_number] => 12112679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8104961 [patent_doc_number] => 08154130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby' [patent_app_type] => utility [patent_app_number] => 12/107992 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4514 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154130.pdf [firstpage_image] =>[orig_patent_app_number] => 12107992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4822162 [patent_doc_number] => 20080227283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 12/108001 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20080227283.pdf [firstpage_image] =>[orig_patent_app_number] => 12108001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4952652 [patent_doc_number] => 20080185676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Method for forming STI of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/078967 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1190 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185676.pdf [firstpage_image] =>[orig_patent_app_number] => 12078967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4719462 [patent_doc_number] => 20080241985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Microelectronic imaging units and methods of manufacturing microelectronic imaging units' [patent_app_type] => utility [patent_app_number] => 12/081003 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20080241985.pdf [firstpage_image] =>[orig_patent_app_number] => 12081003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4807843 [patent_doc_number] => 20080171421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE WITH SMOOTHING' [patent_app_type] => utility [patent_app_number] => 12/051502 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3605 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20080171421.pdf [firstpage_image] =>[orig_patent_app_number] => 12051502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749195 [patent_doc_number] => 20080157266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'STI LINER MODIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/049452 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3673 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157266.pdf [firstpage_image] =>[orig_patent_app_number] => 12049452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749190 [patent_doc_number] => 20080157261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/049258 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9829 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157261.pdf [firstpage_image] =>[orig_patent_app_number] => 12049258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4782623 [patent_doc_number] => 20080135952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K DIELECTRIC LAYER AND A METAL GATE ELECTRODE' [patent_app_type] => utility [patent_app_number] => 12/031409 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5181 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135952.pdf [firstpage_image] =>[orig_patent_app_number] => 12031409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4460167 [patent_doc_number] => 07879646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming assemblies displaying differential negative resistance' [patent_app_type] => utility [patent_app_number] => 12/068020 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3996 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/879/07879646.pdf [firstpage_image] =>[orig_patent_app_number] => 12068020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4965380 [patent_doc_number] => 20080108200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Process for self-aligned manufacture of integrated electronic devices' [patent_app_type] => utility [patent_app_number] => 12/006706 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2892 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108200.pdf [firstpage_image] =>[orig_patent_app_number] => 12006706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 348766 [patent_doc_number] => 07494881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Methods for selective placement of dislocation arrays' [patent_app_type] => utility [patent_app_number] => 11/945130 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12441 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494881.pdf [firstpage_image] =>[orig_patent_app_number] => 11945130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5275488 [patent_doc_number] => 20090127620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE' [patent_app_type] => utility [patent_app_number] => 11/941129 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127620.pdf [firstpage_image] =>[orig_patent_app_number] => 11941129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5410170 [patent_doc_number] => 20090124069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION' [patent_app_type] => utility [patent_app_number] => 11/939578 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20090124069.pdf [firstpage_image] =>[orig_patent_app_number] => 11939578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4507266 [patent_doc_number] => 07915169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Processes for forming electronic devices including polishing metal-containing layers' [patent_app_type] => utility [patent_app_number] => 11/934628 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6561 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915169.pdf [firstpage_image] =>[orig_patent_app_number] => 11934628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5265035 [patent_doc_number] => 20090117720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS' [patent_app_type] => utility [patent_app_number] => 11/934479 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4836 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117720.pdf [firstpage_image] =>[orig_patent_app_number] => 11934479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4876778 [patent_doc_number] => 20080150161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process' [patent_app_type] => utility [patent_app_number] => 11/934009 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3308 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150161.pdf [firstpage_image] =>[orig_patent_app_number] => 11934009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9239780 [patent_doc_number] => 08604575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'X-Y address type solid state image pickup device and method of producing the same' [patent_app_type] => utility [patent_app_number] => 11/981389 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11981389 [rel_patent_id] =>[rel_patent_doc_number] =>)