Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 162265
[patent_doc_number] => 07670886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method for fabricating polysilicon film'
[patent_app_type] => utility
[patent_app_number] => 11/472858
[patent_app_country] => US
[patent_app_date] => 2006-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2268
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/670/07670886.pdf
[firstpage_image] =>[orig_patent_app_number] => 11472858
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/472858 | Method for fabricating polysilicon film | Jun 21, 2006 | Issued |
Array
(
[id] => 5730240
[patent_doc_number] => 20060255354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/455950
[patent_app_country] => US
[patent_app_date] => 2006-06-20
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[pdf_file] => publications/A1/0255/20060255354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11455950
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/455950 | Semiconductor device and method for manufacturing the same | Jun 19, 2006 | Issued |
Array
(
[id] => 363434
[patent_doc_number] => 07482245
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-27
[patent_title] => 'Stress profile modulation in STI gap fill'
[patent_app_type] => utility
[patent_app_number] => 11/471958
[patent_app_country] => US
[patent_app_date] => 2006-06-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/482/07482245.pdf
[firstpage_image] =>[orig_patent_app_number] => 11471958
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/471958 | Stress profile modulation in STI gap fill | Jun 19, 2006 | Issued |
Array
(
[id] => 352605
[patent_doc_number] => 07491626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-17
[patent_title] => 'Layer growth using metal film and/or islands'
[patent_app_type] => utility
[patent_app_number] => 11/424999
[patent_app_country] => US
[patent_app_date] => 2006-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5387
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[pdf_file] => patents/07/491/07491626.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424999
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424999 | Layer growth using metal film and/or islands | Jun 18, 2006 | Issued |
Array
(
[id] => 5019578
[patent_doc_number] => 20070145544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Method for producing a grid cap with a locally increased dielectric constant'
[patent_app_type] => utility
[patent_app_number] => 11/454468
[patent_app_country] => US
[patent_app_date] => 2006-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4755
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[pdf_file] => publications/A1/0145/20070145544.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454468
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454468 | Method for producing a grid cap with a locally increased dielectric constant | Jun 15, 2006 | Issued |
Array
(
[id] => 5141954
[patent_doc_number] => 20070004170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/451519
[patent_app_country] => US
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[pdf_file] => publications/A1/0004/20070004170.pdf
[firstpage_image] =>[orig_patent_app_number] => 11451519
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451519 | Method of manufacturing semiconductor device | Jun 12, 2006 | Issued |
Array
(
[id] => 585145
[patent_doc_number] => 07442620
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[patent_issue_date] => 2008-10-28
[patent_title] => 'Methods for forming a trench isolation structure with rounded corners in a silicon substrate'
[patent_app_type] => utility
[patent_app_number] => 11/423859
[patent_app_country] => US
[patent_app_date] => 2006-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3174
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/442/07442620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11423859
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423859 | Methods for forming a trench isolation structure with rounded corners in a silicon substrate | Jun 12, 2006 | Issued |
Array
(
[id] => 5165687
[patent_doc_number] => 20070287274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'Implantation of carbon and/or fluorine in NMOS fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/451919
[patent_app_country] => US
[patent_app_date] => 2006-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3312
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[pdf_file] => publications/A1/0287/20070287274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11451919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451919 | Implantation of carbon and/or fluorine in NMOS fabrication | Jun 12, 2006 | Issued |
Array
(
[id] => 4999924
[patent_doc_number] => 20070042558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-22
[patent_title] => 'Process for manufacturing a high-quality SOI wafer'
[patent_app_type] => utility
[patent_app_number] => 11/448589
[patent_app_country] => US
[patent_app_date] => 2006-06-06
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[pdf_file] => publications/A1/0042/20070042558.pdf
[firstpage_image] =>[orig_patent_app_number] => 11448589
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/448589 | Process for manufacturing a high-quality SOI wafer | Jun 5, 2006 | Issued |
Array
(
[id] => 5697564
[patent_doc_number] => 20060214248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Single crystal silicon sensor with additional layer and method of producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/445549
[patent_app_country] => US
[patent_app_date] => 2006-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3073
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[pdf_file] => publications/A1/0214/20060214248.pdf
[firstpage_image] =>[orig_patent_app_number] => 11445549
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/445549 | Single crystal silicon sensor with additional layer and method of producing the same | Jun 1, 2006 | Issued |
Array
(
[id] => 5750926
[patent_doc_number] => 20060220075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Methods of fabricating self-aligned source of flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/446064
[patent_app_country] => US
[patent_app_date] => 2006-06-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20060220075.pdf
[firstpage_image] =>[orig_patent_app_number] => 11446064
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/446064 | Methods of fabricating self-aligned source of flash memory device | May 31, 2006 | Abandoned |
Array
(
[id] => 322543
[patent_doc_number] => 07517775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'Methods of selective deposition of heavily doped epitaxial SiGe'
[patent_app_type] => utility
[patent_app_number] => 11/420906
[patent_app_country] => US
[patent_app_date] => 2006-05-30
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[pdf_file] => patents/07/517/07517775.pdf
[firstpage_image] =>[orig_patent_app_number] => 11420906
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420906 | Methods of selective deposition of heavily doped epitaxial SiGe | May 29, 2006 | Issued |
Array
(
[id] => 5010956
[patent_doc_number] => 20070281435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'ENGINEERING STRAIN IN THICK STRAINED-SOI SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 11/420849
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[firstpage_image] =>[orig_patent_app_number] => 11420849
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420849 | Engineering strain in thick strained-SOI substrates | May 29, 2006 | Issued |
Array
(
[id] => 579149
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[patent_title] => 'Formation of improved SOI substrates using bulk semiconductor wafers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420279 | Formation of improved SOI substrates using bulk semiconductor wafers | May 24, 2006 | Issued |
Array
(
[id] => 5599589
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[patent_title] => 'Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438846 | Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device | May 22, 2006 | Abandoned |
Array
(
[id] => 4476857
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[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438066 | Semiconductor device and manufacturing method thereof | May 21, 2006 | Issued |
Array
(
[id] => 224890
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[patent_title] => 'Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures'
[patent_app_type] => utility
[patent_app_number] => 11/437319
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/437319 | Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures | May 18, 2006 | Issued |
Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411828 | SOI substrate with selective oxide layer thickness control | Apr 26, 2006 | Abandoned |