Koosha Sharifi-tafreshi

Array ( [id] => 5869033 [patent_doc_number] => 20060163650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Power semiconductor device with endless gate trenches' [patent_app_type] => utility [patent_app_number] => 11/338215 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1420 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163650.pdf [firstpage_image] =>[orig_patent_app_number] => 11338215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5874572 [patent_doc_number] => 20060166471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Memory apparatus and production method' [patent_app_type] => utility [patent_app_number] => 11/329659 [patent_app_country] => US [patent_app_date] => 2006-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3505 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166471.pdf [firstpage_image] =>[orig_patent_app_number] => 11329659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631717 [patent_doc_number] => 20060148187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Self-aligned bipolar semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/320579 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2097 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148187.pdf [firstpage_image] =>[orig_patent_app_number] => 11320579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631749 [patent_doc_number] => 20060148219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for photomask processing' [patent_app_type] => utility [patent_app_number] => 11/320589 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1357 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148219.pdf [firstpage_image] =>[orig_patent_app_number] => 11320589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631728 [patent_doc_number] => 20060148198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for forming device isolation region in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/320339 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1981 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148198.pdf [firstpage_image] =>[orig_patent_app_number] => 11320339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5022960 [patent_doc_number] => 20070148926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors' [patent_app_type] => utility [patent_app_number] => 11/321128 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148926.pdf [firstpage_image] =>[orig_patent_app_number] => 11321128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 803255 [patent_doc_number] => 07422959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Method for forming isolation trench in a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/319228 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1752 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/422/07422959.pdf [firstpage_image] =>[orig_patent_app_number] => 11319228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7967545 [patent_doc_number] => 07939841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'High output light emitting diode and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/318505 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 4005 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939841.pdf [firstpage_image] =>[orig_patent_app_number] => 11318505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7741846 [patent_doc_number] => 08106437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/311165 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 4969 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106437.pdf [firstpage_image] =>[orig_patent_app_number] => 11311165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 363444 [patent_doc_number] => 07482255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method of ion implantation to reduce transient enhanced diffusion' [patent_app_type] => utility [patent_app_number] => 11/302499 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4840 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482255.pdf [firstpage_image] =>[orig_patent_app_number] => 11302499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5807812 [patent_doc_number] => 20060094167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Embedded ROM device using substrate leakage' [patent_app_type] => utility [patent_app_number] => 11/298011 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5596 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094167.pdf [firstpage_image] =>[orig_patent_app_number] => 11298011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5913048 [patent_doc_number] => 20060128110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/297488 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8762 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128110.pdf [firstpage_image] =>[orig_patent_app_number] => 11297488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 236271 [patent_doc_number] => 07595252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/295359 [patent_app_country] => US [patent_app_date] => 2005-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2291 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595252.pdf [firstpage_image] =>[orig_patent_app_number] => 11295359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5814239 [patent_doc_number] => 20060084246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Manufacturing method for crystalline semiconductor material and manufacturing method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/293727 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5864 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20060084246.pdf [firstpage_image] =>[orig_patent_app_number] => 11293727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 852951 [patent_doc_number] => 07378335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Plasma implantation of deuterium for passivation of semiconductor-device interfaces' [patent_app_type] => utility [patent_app_number] => 11/288828 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378335.pdf [firstpage_image] =>[orig_patent_app_number] => 11288828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4982900 [patent_doc_number] => 20070087458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Semiconductor device and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 10/579239 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087458.pdf [firstpage_image] =>[orig_patent_app_number] => 10579239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 352611 [patent_doc_number] => 07491632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Buried subcollector for high frequency passive semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/164108 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3824 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491632.pdf [firstpage_image] =>[orig_patent_app_number] => 11164108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7689406 [patent_doc_number] => 20070105292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Method for fabricating high tensile stress film and strained-silicon transistors' [patent_app_type] => utility [patent_app_number] => 11/163988 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2468 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105292.pdf [firstpage_image] =>[orig_patent_app_number] => 11163988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 672116 [patent_doc_number] => 07091128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs' [patent_app_type] => utility [patent_app_number] => 11/266855 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 3781 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091128.pdf [firstpage_image] =>[orig_patent_app_number] => 11266855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5828360 [patent_doc_number] => 20060063377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Methods for creating electrophoretically insulated vias in semiconductive substrates' [patent_app_type] => utility [patent_app_number] => 11/266837 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4079 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063377.pdf [firstpage_image] =>[orig_patent_app_number] => 11266837 [rel_patent_id] =>[rel_patent_doc_number] =>)