Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5793719
[patent_doc_number] => 20060014400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Method for fabricating a buried metallic layer in a semiconductor body and semiconductor component having a buried metallic layer'
[patent_app_type] => utility
[patent_app_number] => 11/153239
[patent_app_country] => US
[patent_app_date] => 2005-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7175
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20060014400.pdf
[firstpage_image] =>[orig_patent_app_number] => 11153239
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/153239 | Method for fabricating a buried metallic layer in a semiconductor body and semiconductor component having a buried metallic layer | Jun 14, 2005 | Issued |
Array
(
[id] => 7248152
[patent_doc_number] => 20050272243
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-08
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/142439
[patent_app_country] => US
[patent_app_date] => 2005-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3874
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[pdf_file] => publications/A1/0272/20050272243.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142439
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142439 | Method of manufacturing semiconductor device | Jun 1, 2005 | Abandoned |
Array
(
[id] => 67630
[patent_doc_number] => RE041426
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2010-07-13
[patent_title] => 'Manufacturing methods of liquid crystal displays'
[patent_app_type] => reissue
[patent_app_number] => 11/141675
[patent_app_country] => US
[patent_app_date] => 2005-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 30
[patent_no_of_words] => 4205
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => -9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/041/RE041426.pdf
[firstpage_image] =>[orig_patent_app_number] => 11141675
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/141675 | Manufacturing methods of liquid crystal displays | May 30, 2005 | Issued |
Array
(
[id] => 7221507
[patent_doc_number] => 20050260862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Semiconductor device and method for producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/132258
[patent_app_country] => US
[patent_app_date] => 2005-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5280
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20050260862.pdf
[firstpage_image] =>[orig_patent_app_number] => 11132258
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/132258 | Semiconductor device and method for producing the same | May 18, 2005 | Issued |
Array
(
[id] => 548171
[patent_doc_number] => 07170131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-30
[patent_title] => 'Flash memory array with increased coupling between floating and control gates'
[patent_app_type] => utility
[patent_app_number] => 11/132522
[patent_app_country] => US
[patent_app_date] => 2005-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 7053
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/170/07170131.pdf
[firstpage_image] =>[orig_patent_app_number] => 11132522
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/132522 | Flash memory array with increased coupling between floating and control gates | May 17, 2005 | Issued |
Array
(
[id] => 370197
[patent_doc_number] => 07476972
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Circuit device, manufacturing method thereof, and sheet-like board member'
[patent_app_type] => utility
[patent_app_number] => 11/131638
[patent_app_country] => US
[patent_app_date] => 2005-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 8224
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/476/07476972.pdf
[firstpage_image] =>[orig_patent_app_number] => 11131638
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/131638 | Circuit device, manufacturing method thereof, and sheet-like board member | May 16, 2005 | Issued |
Array
(
[id] => 833432
[patent_doc_number] => 07396721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Method of fabricating a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/130128
[patent_app_country] => US
[patent_app_date] => 2005-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 27
[patent_no_of_words] => 6624
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/396/07396721.pdf
[firstpage_image] =>[orig_patent_app_number] => 11130128
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/130128 | Method of fabricating a semiconductor device | May 16, 2005 | Issued |
Array
(
[id] => 5614027
[patent_doc_number] => 20060115955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'METHOD FOR MANUFACTURING ANTI-PUNCH THROUGH SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 10/908379
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2165
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20060115955.pdf
[firstpage_image] =>[orig_patent_app_number] => 10908379
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/908379 | Method for manufacturing anti-punch through semiconductor device | May 9, 2005 | Issued |
Array
(
[id] => 5834851
[patent_doc_number] => 20060246682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'PRODUCT AND METHOD FOR INTEGRATION OF DEEP TRENCH MESH AND STRUCTURES UNDER A BOND PAD'
[patent_app_type] => utility
[patent_app_number] => 10/908118
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2488
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20060246682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10908118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/908118 | Product and method for integration of deep trench mesh and structures under a bond pad | Apr 27, 2005 | Issued |
Array
(
[id] => 864453
[patent_doc_number] => 07368302
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Dynamic metal fill for correcting non-planar region'
[patent_app_type] => utility
[patent_app_number] => 10/908128
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5220
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/368/07368302.pdf
[firstpage_image] =>[orig_patent_app_number] => 10908128
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/908128 | Dynamic metal fill for correcting non-planar region | Apr 27, 2005 | Issued |
Array
(
[id] => 5922880
[patent_doc_number] => 20060240635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-26
[patent_title] => 'Self-aligned STI SONOS'
[patent_app_type] => utility
[patent_app_number] => 11/113509
[patent_app_country] => US
[patent_app_date] => 2005-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0240/20060240635.pdf
[firstpage_image] =>[orig_patent_app_number] => 11113509
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/113509 | Self-aligned STI SONOS | Apr 24, 2005 | Issued |
Array
(
[id] => 7069658
[patent_doc_number] => 20050245043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/110359
[patent_app_country] => US
[patent_app_date] => 2005-04-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0245/20050245043.pdf
[firstpage_image] =>[orig_patent_app_number] => 11110359
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/110359 | Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit | Apr 19, 2005 | Issued |
Array
(
[id] => 5859073
[patent_doc_number] => 20060228867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Isolation region formation that controllably induces stress in active regions'
[patent_app_type] => utility
[patent_app_number] => 11/104038
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11104038
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/104038 | Isolation region formation that controllably induces stress in active regions | Apr 11, 2005 | Abandoned |
Array
(
[id] => 5859066
[patent_doc_number] => 20060228864
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[patent_title] => 'Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process'
[patent_app_type] => utility
[patent_app_number] => 11/103948
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103948 | Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process | Apr 11, 2005 | Abandoned |
Array
(
[id] => 5738541
[patent_doc_number] => 20060008932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Liquid crystal display device having driving circuit and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/099519
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[patent_app_date] => 2005-04-06
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[firstpage_image] =>[orig_patent_app_number] => 11099519
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099519 | Liquid crystal display device having driving circuit and method of fabricating the same | Apr 5, 2005 | Issued |
Array
(
[id] => 383050
[patent_doc_number] => 07307002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-11
[patent_title] => 'Non-critical complementary masking method for poly-1 definition in flash memory device fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/099339
[patent_app_country] => US
[patent_app_date] => 2005-04-04
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[pdf_file] => patents/07/307/07307002.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099339
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099339 | Non-critical complementary masking method for poly-1 definition in flash memory device fabrication | Apr 3, 2005 | Issued |
Array
(
[id] => 7229982
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[patent_country] => US
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[patent_issue_date] => 2005-11-17
[patent_title] => 'Semiconductor device including isolation trench and method for fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095569 | Semiconductor device including isolation trench and method for fabricating the same | Mar 31, 2005 | Abandoned |
Array
(
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[patent_title] => 'Method for manufacturing silicon-on-insulator wafer'
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Array
(
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[patent_title] => 'Method of manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/090839 | Method of manufacturing a semiconductor device with a shallow trench isolation structure | Mar 24, 2005 | Issued |
Array
(
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[patent_title] => 'Method and structure for reducing contact aspect ratios'
[patent_app_type] => utility
[patent_app_number] => 11/088311
[patent_app_country] => US
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[pdf_file] => patents/07/268/07268072.pdf
[firstpage_image] =>[orig_patent_app_number] => 11088311
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/088311 | Method and structure for reducing contact aspect ratios | Mar 22, 2005 | Issued |