Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1037904
[patent_doc_number] => 06873056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-29
[patent_title] => 'Electrode-to-electrode bond structure'
[patent_app_type] => utility
[patent_app_number] => 10/704553
[patent_app_country] => US
[patent_app_date] => 2003-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/873/06873056.pdf
[firstpage_image] =>[orig_patent_app_number] => 10704553
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/704553 | Electrode-to-electrode bond structure | Nov 11, 2003 | Issued |
Array
(
[id] => 662947
[patent_doc_number] => 07101801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Method of manufacturing semiconductor device using chemical mechanical polishing'
[patent_app_type] => utility
[patent_app_number] => 10/704628
[patent_app_country] => US
[patent_app_date] => 2003-11-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/101/07101801.pdf
[firstpage_image] =>[orig_patent_app_number] => 10704628
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/704628 | Method of manufacturing semiconductor device using chemical mechanical polishing | Nov 11, 2003 | Issued |
Array
(
[id] => 1037511
[patent_doc_number] => 06872660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-29
[patent_title] => 'Methods of forming conductive contacts'
[patent_app_type] => utility
[patent_app_number] => 10/703778
[patent_app_country] => US
[patent_app_date] => 2003-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 10703778
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/703778 | Methods of forming conductive contacts | Nov 6, 2003 | Issued |
Array
(
[id] => 1085598
[patent_doc_number] => 06830943
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-14
[patent_title] => 'Thin film CMOS calibration standard having protective cover layer'
[patent_app_type] => B1
[patent_app_number] => 10/702165
[patent_app_country] => US
[patent_app_date] => 2003-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/06/830/06830943.pdf
[firstpage_image] =>[orig_patent_app_number] => 10702165
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/702165 | Thin film CMOS calibration standard having protective cover layer | Nov 3, 2003 | Issued |
Array
(
[id] => 1110918
[patent_doc_number] => 06806141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Field effect transistor with gate layer and method of making same'
[patent_app_type] => B2
[patent_app_number] => 10/696838
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[patent_app_date] => 2003-10-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/806/06806141.pdf
[firstpage_image] =>[orig_patent_app_number] => 10696838
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/696838 | Field effect transistor with gate layer and method of making same | Oct 29, 2003 | Issued |
Array
(
[id] => 7365195
[patent_doc_number] => 20040092084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Method for treating a semiconductor material for subsequent bonding'
[patent_app_type] => new
[patent_app_number] => 10/695938
[patent_app_country] => US
[patent_app_date] => 2003-10-30
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[pdf_file] => publications/A1/0092/20040092084.pdf
[firstpage_image] =>[orig_patent_app_number] => 10695938
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/695938 | Method for ion treating a semiconductor material for subsequent bonding | Oct 29, 2003 | Issued |
Array
(
[id] => 7189839
[patent_doc_number] => 20040084751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Inductive storage capacitor'
[patent_app_type] => new
[patent_app_number] => 10/694661
[patent_app_country] => US
[patent_app_date] => 2003-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[patent_no_of_words] => 9697
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[pdf_file] => publications/A1/0084/20040084751.pdf
[firstpage_image] =>[orig_patent_app_number] => 10694661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/694661 | Inductive storage capacitor | Oct 26, 2003 | Abandoned |
Array
(
[id] => 7287232
[patent_doc_number] => 20040147067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Semiconductor apparatus and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/690840
[patent_app_country] => US
[patent_app_date] => 2003-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 7402
[patent_no_of_claims] => 27
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[pdf_file] => publications/A1/0147/20040147067.pdf
[firstpage_image] =>[orig_patent_app_number] => 10690840
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/690840 | Methods for manufacturing an active matrix display device | Oct 22, 2003 | Issued |
Array
(
[id] => 944102
[patent_doc_number] => 06967156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-22
[patent_title] => 'Method to fabricate aligned dual damascene openings'
[patent_app_type] => utility
[patent_app_number] => 10/690998
[patent_app_country] => US
[patent_app_date] => 2003-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/967/06967156.pdf
[firstpage_image] =>[orig_patent_app_number] => 10690998
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/690998 | Method to fabricate aligned dual damascene openings | Oct 21, 2003 | Issued |
Array
(
[id] => 7304930
[patent_doc_number] => 20040115891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Process and installation for doping an etched pattern of resistive elements'
[patent_app_type] => new
[patent_app_number] => 10/689528
[patent_app_country] => US
[patent_app_date] => 2003-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3528
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[pdf_file] => publications/A1/0115/20040115891.pdf
[firstpage_image] =>[orig_patent_app_number] => 10689528
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/689528 | Process and installation for doping an etched pattern of resistive elements | Oct 19, 2003 | Issued |
Array
(
[id] => 759181
[patent_doc_number] => 07015527
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Metal oxynitride capacitor barrier layer'
[patent_app_type] => utility
[patent_app_number] => 10/688678
[patent_app_country] => US
[patent_app_date] => 2003-10-17
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[pdf_file] => patents/07/015/07015527.pdf
[firstpage_image] =>[orig_patent_app_number] => 10688678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/688678 | Metal oxynitride capacitor barrier layer | Oct 16, 2003 | Issued |
Array
(
[id] => 557366
[patent_doc_number] => 07157352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Method for producing ultra-thin semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/680548
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[firstpage_image] =>[orig_patent_app_number] => 10680548
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680548 | Method for producing ultra-thin semiconductor device | Oct 6, 2003 | Issued |
Array
(
[id] => 988126
[patent_doc_number] => 06921681
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[patent_issue_date] => 2005-07-26
[patent_title] => 'Process for manufacturing photosensitive module'
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[pdf_file] => patents/06/921/06921681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681458
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681458 | Process for manufacturing photosensitive module | Oct 6, 2003 | Issued |
Array
(
[id] => 931141
[patent_doc_number] => 06979645
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[patent_kind] => B2
[patent_issue_date] => 2005-12-27
[patent_title] => 'Method of producing a semiconductor device having copper wiring'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/979/06979645.pdf
[firstpage_image] =>[orig_patent_app_number] => 10680668
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680668 | Method of producing a semiconductor device having copper wiring | Oct 6, 2003 | Issued |
Array
(
[id] => 1134141
[patent_doc_number] => 06784052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'Method of forming a capacitor with two diffusion barrier layers formed in the same step'
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[firstpage_image] =>[orig_patent_app_number] => 10676498
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676498 | Method of forming a capacitor with two diffusion barrier layers formed in the same step | Sep 29, 2003 | Issued |
Array
(
[id] => 542452
[patent_doc_number] => 07169713
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[patent_title] => 'Atomic layer deposition (ALD) method with enhanced deposition rate'
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[pdf_file] => patents/07/169/07169713.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672778
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672778 | Atomic layer deposition (ALD) method with enhanced deposition rate | Sep 25, 2003 | Issued |
Array
(
[id] => 677117
[patent_doc_number] => 07087977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Semiconductor device including multiple wiring layers and circuits operating in different frequency bands'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/670258 | Semiconductor device including multiple wiring layers and circuits operating in different frequency bands | Sep 25, 2003 | Issued |
Array
(
[id] => 7116747
[patent_doc_number] => 20050070048
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[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Devices and methods employing high thermal conductivity heat dissipation substrates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672968 | Devices and methods employing high thermal conductivity heat dissipation substrates | Sep 24, 2003 | Abandoned |
Array
(
[id] => 7010920
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[patent_title] => 'Method and apparatus for fabricating CMOS field effect transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/669898 | Method and apparatus for fabricating CMOS field effect transistors | Sep 23, 2003 | Issued |
Array
(
[id] => 7008350
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[patent_title] => 'Semiconductor devices having regions of induced high and low conductivity, and methods of making the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/671303 | Semiconductor devices having regions of induced high and low conductivity, and methods of making the same | Sep 23, 2003 | Issued |