Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6787769
[patent_doc_number] => 20030139008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/216358
[patent_app_country] => US
[patent_app_date] => 2002-08-12
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[pdf_file] => publications/A1/0139/20030139008.pdf
[firstpage_image] =>[orig_patent_app_number] => 10216358
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/216358 | Providing a conductive material in an opening | Aug 11, 2002 | Issued |
Array
(
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[patent_doc_number] => 20040029377
[patent_country] => US
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[patent_issue_date] => 2004-02-12
[patent_title] => 'Refractory metal nitride barrier layer with gradient nitrogen concentration'
[patent_app_type] => new
[patent_app_number] => 10/214638
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/214638 | Refractory metal nitride barrier layer with gradient nitrogen concentration | Aug 7, 2002 | Issued |
Array
(
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[patent_doc_number] => 06716753
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Method for forming a self-passivated copper interconnect structure'
[patent_app_type] => B1
[patent_app_number] => 10/207548
[patent_app_country] => US
[patent_app_date] => 2002-07-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/207548 | Method for forming a self-passivated copper interconnect structure | Jul 28, 2002 | Issued |
Array
(
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[patent_doc_number] => 20030062565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Semiconductor device and method of fabricating same'
[patent_app_type] => new
[patent_app_number] => 10/202500
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[firstpage_image] =>[orig_patent_app_number] => 10202500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/202500 | Nonvolatile vertical channel semiconductor device | Jul 22, 2002 | Issued |
Array
(
[id] => 6730366
[patent_doc_number] => 20030186556
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[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'METHODS USED IN FABRICATING GATES IN INTEGRATED CIRCUIT DEVICE STRUCTURES'
[patent_app_type] => new
[patent_app_number] => 10/198298
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10198298
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/198298 | Methods used in fabricating gates in integrated circuit device structures | Jul 16, 2002 | Issued |
Array
(
[id] => 1310980
[patent_doc_number] => 06613690
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers'
[patent_app_type] => B1
[patent_app_number] => 10/197318
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[firstpage_image] =>[orig_patent_app_number] => 10197318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197318 | Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers | Jul 16, 2002 | Issued |
Array
(
[id] => 1246725
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[patent_issue_date] => 2004-01-13
[patent_title] => 'Damascene structure using a sacrificial conductive layer'
[patent_app_type] => B2
[patent_app_number] => 10/195763
[patent_app_country] => US
[patent_app_date] => 2002-07-15
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[firstpage_image] =>[orig_patent_app_number] => 10195763
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/195763 | Damascene structure using a sacrificial conductive layer | Jul 14, 2002 | Issued |
Array
(
[id] => 6730368
[patent_doc_number] => 20030186558
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[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Planarization for integrated circuits'
[patent_app_type] => new
[patent_app_number] => 10/195678
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/195678 | Planarization for integrated circuits | Jul 14, 2002 | Issued |
Array
(
[id] => 1155420
[patent_doc_number] => 06764881
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Method for manufacturing electro ceramic components'
[patent_app_type] => B2
[patent_app_number] => 10/193972
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[firstpage_image] =>[orig_patent_app_number] => 10193972
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193972 | Method for manufacturing electro ceramic components | Jul 11, 2002 | Issued |
Array
(
[id] => 1367904
[patent_doc_number] => 06566266
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-20
[patent_title] => 'Method of polishing a layer comprising copper using an oxide inhibitor slurry'
[patent_app_type] => B2
[patent_app_number] => 10/193368
[patent_app_country] => US
[patent_app_date] => 2002-07-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193368 | Method of polishing a layer comprising copper using an oxide inhibitor slurry | Jul 10, 2002 | Issued |
Array
(
[id] => 1110980
[patent_doc_number] => 06806163
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Ion implant method for topographic feature corner rounding'
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[patent_app_number] => 10/190248
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[firstpage_image] =>[orig_patent_app_number] => 10190248
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190248 | Ion implant method for topographic feature corner rounding | Jul 4, 2002 | Issued |
Array
(
[id] => 1095990
[patent_doc_number] => 06821856
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[patent_issue_date] => 2004-11-23
[patent_title] => 'Method of manufacturing semiconductor device having source/drain regions included in a semiconductor layer formed over an isolation insulating film and a semiconductor device fabricated thereby'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/188108 | Method of manufacturing semiconductor device having source/drain regions included in a semiconductor layer formed over an isolation insulating film and a semiconductor device fabricated thereby | Jul 2, 2002 | Issued |
Array
(
[id] => 1130565
[patent_doc_number] => 06787464
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[patent_title] => 'Method of forming silicide layers over a plurality of semiconductor devices'
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Array
(
[id] => 6851566
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[patent_title] => 'Method for fabricating monolithic integrated semiconductor photonic device'
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Array
(
[id] => 6753449
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/180328 | Semiconductor device with trench isolation between two regions having different gate insulating films | Jun 26, 2002 | Issued |
Array
(
[id] => 6824451
[patent_doc_number] => 20030235073
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[patent_issue_date] => 2003-12-25
[patent_title] => 'Memory structures'
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[firstpage_image] =>[orig_patent_app_number] => 10177239
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177239 | Structure of chalcogenide memory element | Jun 20, 2002 | Issued |
Array
(
[id] => 7150197
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[patent_title] => 'Method for producing polymer-free area on a substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/481848 | Method for producing polymer-free area on a substrate | Jun 16, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/166618 | Method for manufacturing semiconductor image sensor with color filters and bonding pads | Jun 11, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/166458 | Multiple leadframe laminated IC package | Jun 9, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/164429 | Co-sputter deposition of metal-doped chalcogenides | Jun 5, 2002 | Issued |