Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6785792
[patent_doc_number] => 20030137031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Semiconductor device having a die with a rhombic shape'
[patent_app_type] => new
[patent_app_number] => 10/052467
[patent_app_country] => US
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[pdf_file] => publications/A1/0137/20030137031.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052467
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052467 | Semiconductor device having a die with a rhombic shape | Jan 22, 2002 | Abandoned |
Array
(
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[patent_doc_number] => 06809376
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[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Semiconductor integrated circuit device and manufacture method therefore'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055717 | Semiconductor integrated circuit device and manufacture method therefore | Jan 22, 2002 | Issued |
Array
(
[id] => 1254258
[patent_doc_number] => 06670669
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[patent_issue_date] => 2003-12-30
[patent_title] => 'Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate'
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[patent_app_number] => 10/030117
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/030117 | Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate | Jan 22, 2002 | Issued |
Array
(
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[patent_doc_number] => 06664172
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[patent_issue_date] => 2003-12-16
[patent_title] => 'Method of forming a MOS transistor with improved threshold voltage stability'
[patent_app_type] => B2
[patent_app_number] => 09/683578
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[patent_app_date] => 2002-01-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/683578 | Method of forming a MOS transistor with improved threshold voltage stability | Jan 21, 2002 | Issued |
Array
(
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[patent_doc_number] => 06803646
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[patent_issue_date] => 2004-10-12
[patent_title] => 'Semiconductor device having first chip secured within resin layer and second chip secured on resin layer'
[patent_app_type] => B2
[patent_app_number] => 10/052078
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052078 | Semiconductor device having first chip secured within resin layer and second chip secured on resin layer | Jan 16, 2002 | Issued |
Array
(
[id] => 6348945
[patent_doc_number] => 20020056880
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[patent_issue_date] => 2002-05-16
[patent_title] => 'Method for fabricating interconnect of capacitor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/045899 | Method for fabricating interconnect of capacitor | Jan 10, 2002 | Abandoned |
Array
(
[id] => 6659627
[patent_doc_number] => 20030134438
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[patent_issue_date] => 2003-07-17
[patent_title] => 'Rare earth metal oxide memory element based on charge storage and method for manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/042181
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[pdf_file] => publications/A1/0134/20030134438.pdf
[firstpage_image] =>[orig_patent_app_number] => 10042181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/042181 | Rare earth metal oxide memory element based on charge storage and method for manufacturing same | Jan 10, 2002 | Issued |
Array
(
[id] => 1420538
[patent_doc_number] => 06521931
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[patent_kind] => B2
[patent_issue_date] => 2003-02-18
[patent_title] => 'Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme'
[patent_app_type] => B2
[patent_app_number] => 10/040447
[patent_app_country] => US
[patent_app_date] => 2002-01-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040447 | Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme | Jan 8, 2002 | Issued |
Array
(
[id] => 6306614
[patent_doc_number] => 20020094613
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[patent_issue_date] => 2002-07-18
[patent_title] => 'Method of manufacturing semiconductor device'
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[patent_app_number] => 10/034498
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/034498 | Method of making a thin film transistor using laser annealing | Jan 2, 2002 | Issued |
Array
(
[id] => 6080985
[patent_doc_number] => 20020081758
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[patent_issue_date] => 2002-06-27
[patent_title] => 'Method of manufacturing semiconductor integrated circuit device'
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[patent_app_number] => 10/025458
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/025458 | Method of manufacturing and testing semiconductor integrated circuit device | Dec 25, 2001 | Issued |
Array
(
[id] => 1209307
[patent_doc_number] => 06713357
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[patent_title] => 'Method to reduce parasitic capacitance of MOS transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/023348 | Method to reduce parasitic capacitance of MOS transistors | Dec 19, 2001 | Issued |
Array
(
[id] => 1089118
[patent_doc_number] => 06828199
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[patent_title] => 'Monos device having buried metal silicide bit line'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/022798 | Monos device having buried metal silicide bit line | Dec 19, 2001 | Issued |
Array
(
[id] => 1277963
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[patent_title] => 'Formation of a vertical junction throuph process simulation based optimization of implant doses and energies'
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Array
(
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Array
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Array
(
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[patent_title] => 'Techniques for improving adhesion of silicon dioxide to titanium'
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/997965 | Methods of forming capacitors | Nov 28, 2001 | Issued |