Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6890554
[patent_doc_number] => 20010007785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-12
[patent_title] => 'Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells'
[patent_app_type] => new-utility
[patent_app_number] => 09/788248
[patent_app_country] => US
[patent_app_date] => 2001-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2046
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20010007785.pdf
[firstpage_image] =>[orig_patent_app_number] => 09788248
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/788248 | Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells | Feb 14, 2001 | Issued |
Array
(
[id] => 903180
[patent_doc_number] => 07335603
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-26
[patent_title] => 'System and method for fabricating logic devices comprising carbon nanotube transistors'
[patent_app_type] => utility
[patent_app_number] => 09/779374
[patent_app_country] => US
[patent_app_date] => 2001-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 22
[patent_no_of_words] => 9483
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/335/07335603.pdf
[firstpage_image] =>[orig_patent_app_number] => 09779374
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/779374 | System and method for fabricating logic devices comprising carbon nanotube transistors | Feb 6, 2001 | Issued |
Array
(
[id] => 6155666
[patent_doc_number] => 20020145904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Inductive storage capacitor'
[patent_app_type] => new
[patent_app_number] => 09/776003
[patent_app_country] => US
[patent_app_date] => 2001-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9706
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 9
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20020145904.pdf
[firstpage_image] =>[orig_patent_app_number] => 09776003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/776003 | Inductive storage capacitor | Feb 1, 2001 | Issued |
Array
(
[id] => 1440967
[patent_doc_number] => 06495865
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-17
[patent_title] => 'Microcathode with integrated extractor'
[patent_app_type] => B2
[patent_app_number] => 09/775098
[patent_app_country] => US
[patent_app_date] => 2001-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6120
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/495/06495865.pdf
[firstpage_image] =>[orig_patent_app_number] => 09775098
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775098 | Microcathode with integrated extractor | Jan 31, 2001 | Issued |
Array
(
[id] => 7643516
[patent_doc_number] => 06429525
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-08-06
[patent_title] => 'Interconnect structure having improved resist adhesion'
[patent_app_type] => B2
[patent_app_number] => 09/775178
[patent_app_country] => US
[patent_app_date] => 2001-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3820
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429525.pdf
[firstpage_image] =>[orig_patent_app_number] => 09775178
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775178 | Interconnect structure having improved resist adhesion | Jan 31, 2001 | Issued |
Array
(
[id] => 1603215
[patent_doc_number] => 06433395
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Electrostatic discharge protection for salicided devices'
[patent_app_type] => B1
[patent_app_number] => 09/772463
[patent_app_country] => US
[patent_app_date] => 2001-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2855
[patent_no_of_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/433/06433395.pdf
[firstpage_image] =>[orig_patent_app_number] => 09772463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/772463 | Electrostatic discharge protection for salicided devices | Jan 28, 2001 | Issued |
Array
(
[id] => 7639763
[patent_doc_number] => 06396153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-28
[patent_title] => 'Circuit chip package and fabrication method'
[patent_app_type] => B2
[patent_app_number] => 09/768598
[patent_app_country] => US
[patent_app_date] => 2001-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 26
[patent_no_of_words] => 3246
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/396/06396153.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768598 | Circuit chip package and fabrication method | Jan 24, 2001 | Issued |
Array
(
[id] => 1476417
[patent_doc_number] => 06388327
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Capping layer for improved silicide formation in narrow semiconductor structures'
[patent_app_type] => B1
[patent_app_number] => 09/756938
[patent_app_country] => US
[patent_app_date] => 2001-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 23
[patent_no_of_words] => 3015
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/388/06388327.pdf
[firstpage_image] =>[orig_patent_app_number] => 09756938
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/756938 | Capping layer for improved silicide formation in narrow semiconductor structures | Jan 8, 2001 | Issued |
Array
(
[id] => 1398720
[patent_doc_number] => 06537871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-25
[patent_title] => 'Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor'
[patent_app_type] => B2
[patent_app_number] => 09/742568
[patent_app_country] => US
[patent_app_date] => 2000-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 5800
[patent_no_of_claims] => 24
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/537/06537871.pdf
[firstpage_image] =>[orig_patent_app_number] => 09742568
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/742568 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Dec 19, 2000 | Issued |
Array
(
[id] => 6876320
[patent_doc_number] => 20010006473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-05
[patent_title] => 'Nonvolatile ferroelectric memory device and method for fabricating the same'
[patent_app_type] => new-utility
[patent_app_number] => 09/739753
[patent_app_country] => US
[patent_app_date] => 2000-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 10724
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20010006473.pdf
[firstpage_image] =>[orig_patent_app_number] => 09739753
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739753 | Nonvolatile ferroelectric memory device and method for fabricating the same | Dec 19, 2000 | Issued |
Array
(
[id] => 6877577
[patent_doc_number] => 20010003063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-06-07
[patent_title] => 'Electrochemical cobalt silicide liner for metal contact fills and damascene processes'
[patent_app_type] => new-utility
[patent_app_number] => 09/740189
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3511
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20010003063.pdf
[firstpage_image] =>[orig_patent_app_number] => 09740189
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740189 | Electrochemical cobalt silicide liner for metal contact fills and damascene processes | Dec 18, 2000 | Issued |
Array
(
[id] => 1480516
[patent_doc_number] => 06452227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-17
[patent_title] => 'Semiconductor memory device and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/739258
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/452/06452227.pdf
[firstpage_image] =>[orig_patent_app_number] => 09739258
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739258 | Semiconductor memory device and manufacturing method thereof | Dec 18, 2000 | Issued |
Array
(
[id] => 7640262
[patent_doc_number] => 06395652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-05-28
[patent_title] => 'Method of manufacturing thin film transistor'
[patent_app_type] => B2
[patent_app_number] => 09/736308
[patent_app_country] => US
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[pdf_file] => patents/06/395/06395652.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736308
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736308 | Method of manufacturing thin film transistor | Dec 14, 2000 | Issued |
Array
(
[id] => 6875290
[patent_doc_number] => 20010000493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-04-26
[patent_title] => 'Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures'
[patent_app_type] => new-utility
[patent_app_number] => 09/730648
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09730648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/730648 | Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures | Dec 4, 2000 | Issued |
Array
(
[id] => 1285182
[patent_doc_number] => 06638836
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Process for manufacturing a group comprising at least two elements, one whereof includes an encapsulated micro-integrated structure, and thereby obtained group'
[patent_app_type] => B1
[patent_app_number] => 09/727608
[patent_app_country] => US
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[pdf_file] => patents/06/638/06638836.pdf
[firstpage_image] =>[orig_patent_app_number] => 09727608
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/727608 | Process for manufacturing a group comprising at least two elements, one whereof includes an encapsulated micro-integrated structure, and thereby obtained group | Nov 29, 2000 | Issued |
Array
(
[id] => 1542811
[patent_doc_number] => 06372660
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Method for patterning a dual damascene with masked implantation'
[patent_app_type] => B1
[patent_app_number] => 09/725068
[patent_app_country] => US
[patent_app_date] => 2000-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/372/06372660.pdf
[firstpage_image] =>[orig_patent_app_number] => 09725068
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/725068 | Method for patterning a dual damascene with masked implantation | Nov 28, 2000 | Issued |
Array
(
[id] => 1553414
[patent_doc_number] => 06348362
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Manufacturing method of photovoltaic device'
[patent_app_type] => B1
[patent_app_number] => 09/722718
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/348/06348362.pdf
[firstpage_image] =>[orig_patent_app_number] => 09722718
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/722718 | Manufacturing method of photovoltaic device | Nov 27, 2000 | Issued |
Array
(
[id] => 1536187
[patent_doc_number] => 06337276
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[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Methods of forming a copper wiring in a semiconductor device using chemical vapor deposition'
[patent_app_type] => B1
[patent_app_number] => 09/721968
[patent_app_country] => US
[patent_app_date] => 2000-11-27
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[firstpage_image] =>[orig_patent_app_number] => 09721968
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/721968 | Methods of forming a copper wiring in a semiconductor device using chemical vapor deposition | Nov 26, 2000 | Issued |
Array
(
[id] => 1340381
[patent_doc_number] => 06593606
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[patent_issue_date] => 2003-07-15
[patent_title] => 'Staggered bitline strapping of a non-volatile memory cell'
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[patent_app_number] => 09/718771
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[firstpage_image] =>[orig_patent_app_number] => 09718771
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/718771 | Staggered bitline strapping of a non-volatile memory cell | Nov 21, 2000 | Issued |
Array
(
[id] => 1502367
[patent_doc_number] => 06486543
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Packaged semiconductor device having bent leads'
[patent_app_type] => B1
[patent_app_number] => 09/700631
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486543.pdf
[firstpage_image] =>[orig_patent_app_number] => 09700631
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/700631 | Packaged semiconductor device having bent leads | Nov 16, 2000 | Issued |