Search

Koosha Sharifi-tafreshi

Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )

Most Active Art Unit
2623
Art Unit(s)
2623, 2629, 2695
Total Applications
1151
Issued Applications
889
Pending Applications
55
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
09/677268 Integrated photodetector Oct 1, 2000 Abandoned
Array ( [id] => 4351076 [patent_doc_number] => 06291347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method and system for constructing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/671328 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1812 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291347.pdf [firstpage_image] =>[orig_patent_app_number] => 671328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671328
Method and system for constructing semiconductor devices Sep 25, 2000 Issued
Array ( [id] => 1561900 [patent_doc_number] => 06437445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Niobium-near noble metal contact structures for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/670171 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3955 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437445.pdf [firstpage_image] =>[orig_patent_app_number] => 09670171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670171
Niobium-near noble metal contact structures for integrated circuits Sep 25, 2000 Issued
Array ( [id] => 4286928 [patent_doc_number] => 06268268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/667508 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3383 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268268.pdf [firstpage_image] =>[orig_patent_app_number] => 667508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667508
Method of manufacturing semiconductor device Sep 21, 2000 Issued
Array ( [id] => 4267283 [patent_doc_number] => 06306745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Chip-area-efficient pattern and method of hierarchal power routing' [patent_app_type] => 1 [patent_app_number] => 9/666318 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2462 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306745.pdf [firstpage_image] =>[orig_patent_app_number] => 666318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666318
Chip-area-efficient pattern and method of hierarchal power routing Sep 20, 2000 Issued
Array ( [id] => 1398672 [patent_doc_number] => 06537869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/663258 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11410 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537869.pdf [firstpage_image] =>[orig_patent_app_number] => 09663258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663258
Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same Sep 14, 2000 Issued
Array ( [id] => 4377380 [patent_doc_number] => 06303425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/660448 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 131 [patent_no_of_words] => 22413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303425.pdf [firstpage_image] =>[orig_patent_app_number] => 660448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660448
Semiconductor device and method of manufacturing the same Sep 11, 2000 Issued
Array ( [id] => 1520618 [patent_doc_number] => 06413796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Tape for semiconductor package, method of manufacturing the same, and method of manufacturing the package using the tape' [patent_app_type] => B1 [patent_app_number] => 09/652518 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2900 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413796.pdf [firstpage_image] =>[orig_patent_app_number] => 09652518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652518
Tape for semiconductor package, method of manufacturing the same, and method of manufacturing the package using the tape Aug 30, 2000 Issued
Array ( [id] => 1566013 [patent_doc_number] => 06376363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon' [patent_app_type] => B1 [patent_app_number] => 09/645498 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376363.pdf [firstpage_image] =>[orig_patent_app_number] => 09645498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645498
Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon Aug 24, 2000 Issued
Array ( [id] => 7643563 [patent_doc_number] => 06429478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor device which increases the capacity of a capacitor without deepening the contact hole' [patent_app_type] => B1 [patent_app_number] => 09/645061 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6135 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429478.pdf [firstpage_image] =>[orig_patent_app_number] => 09645061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645061
Semiconductor device which increases the capacity of a capacitor without deepening the contact hole Aug 23, 2000 Issued
Array ( [id] => 1485445 [patent_doc_number] => 06365530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Techniques for improving adhesion of silicon dioxide to titanium' [patent_app_type] => B1 [patent_app_number] => 09/645958 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2327 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365530.pdf [firstpage_image] =>[orig_patent_app_number] => 09645958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645958
Techniques for improving adhesion of silicon dioxide to titanium Aug 23, 2000 Issued
Array ( [id] => 1324574 [patent_doc_number] => 06602806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Thermal CVD process for depositing a low dielectric constant carbon-doped silicon oxide film' [patent_app_type] => B1 [patent_app_number] => 09/632668 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 50 [patent_no_of_words] => 16347 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602806.pdf [firstpage_image] =>[orig_patent_app_number] => 09632668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632668
Thermal CVD process for depositing a low dielectric constant carbon-doped silicon oxide film Aug 6, 2000 Issued
Array ( [id] => 1565696 [patent_doc_number] => 06376295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for manufacturing a semiconductor memory device with a fine structure' [patent_app_type] => B1 [patent_app_number] => 09/631977 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 46 [patent_no_of_words] => 10194 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376295.pdf [firstpage_image] =>[orig_patent_app_number] => 09631977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631977
Method for manufacturing a semiconductor memory device with a fine structure Aug 2, 2000 Issued
Array ( [id] => 1561114 [patent_doc_number] => 06362053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide' [patent_app_type] => B1 [patent_app_number] => 09/630933 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362053.pdf [firstpage_image] =>[orig_patent_app_number] => 09630933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630933
Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide Aug 1, 2000 Issued
Array ( [id] => 1433321 [patent_doc_number] => 06340611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/628278 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 123 [patent_no_of_words] => 21180 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340611.pdf [firstpage_image] =>[orig_patent_app_number] => 09628278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628278
Nonvolatile semiconductor memory device Jul 27, 2000 Issued
Array ( [id] => 1497080 [patent_doc_number] => 06404033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/620653 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 1856 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404033.pdf [firstpage_image] =>[orig_patent_app_number] => 09620653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620653
Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication Jul 19, 2000 Issued
Array ( [id] => 1552926 [patent_doc_number] => 06399996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Schottky diode having increased active surface area and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/620074 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1022 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399996.pdf [firstpage_image] =>[orig_patent_app_number] => 09620074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620074
Schottky diode having increased active surface area and method of fabrication Jul 19, 2000 Issued
Array ( [id] => 4377177 [patent_doc_number] => 06303414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method of forming PID protection diode for SOI wafer' [patent_app_type] => 1 [patent_app_number] => 9/614558 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2893 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 480 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303414.pdf [firstpage_image] =>[orig_patent_app_number] => 614558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614558
Method of forming PID protection diode for SOI wafer Jul 11, 2000 Issued
Array ( [id] => 1561167 [patent_doc_number] => 06362080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Formation of a vertical junction through process simulation based optimization of implant doses and energies' [patent_app_type] => B1 [patent_app_number] => 09/614338 [patent_app_country] => US [patent_app_date] => 2000-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2931 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362080.pdf [firstpage_image] =>[orig_patent_app_number] => 09614338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614338
Formation of a vertical junction through process simulation based optimization of implant doses and energies Jul 10, 2000 Issued
Array ( [id] => 1561172 [patent_doc_number] => 06362081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method to improve resistance uniformity and repeatability for low energy ion implantation' [patent_app_type] => B1 [patent_app_number] => 09/611888 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1684 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362081.pdf [firstpage_image] =>[orig_patent_app_number] => 09611888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/611888
Method to improve resistance uniformity and repeatability for low energy ion implantation Jul 6, 2000 Issued
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