Koosha Sharifi-tafreshi
Examiner (ID: 1458, Phone: (571)270-5897 , Office: P/2623 )
Most Active Art Unit | 2623 |
Art Unit(s) | 2623, 2629, 2695 |
Total Applications | 1151 |
Issued Applications | 889 |
Pending Applications | 55 |
Abandoned Applications | 207 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4405660
[patent_doc_number] => 06171898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing'
[patent_app_type] => 1
[patent_app_number] => 9/212031
[patent_app_country] => US
[patent_app_date] => 1998-12-15
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[pdf_file] => patents/06/171/06171898.pdf
[firstpage_image] =>[orig_patent_app_number] => 212031
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212031 | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing | Dec 14, 1998 | Issued |
Array
(
[id] => 4291788
[patent_doc_number] => 06180446
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[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing'
[patent_app_type] => 1
[patent_app_number] => 9/211911
[patent_app_country] => US
[patent_app_date] => 1998-12-15
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[pdf_file] => patents/06/180/06180446.pdf
[firstpage_image] =>[orig_patent_app_number] => 211911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211911 | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing | Dec 14, 1998 | Issued |
Array
(
[id] => 4408514
[patent_doc_number] => 06228699
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Cross leakage of capacitors in DRAM or embedded DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/210703
[patent_app_country] => US
[patent_app_date] => 1998-12-14
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[pdf_file] => patents/06/228/06228699.pdf
[firstpage_image] =>[orig_patent_app_number] => 210703
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/210703 | Cross leakage of capacitors in DRAM or embedded DRAM | Dec 13, 1998 | Issued |
Array
(
[id] => 4182605
[patent_doc_number] => 06150249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Methods of forming niobium-near noble metal contact structures for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/183081
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/150/06150249.pdf
[firstpage_image] =>[orig_patent_app_number] => 183081
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183081 | Methods of forming niobium-near noble metal contact structures for integrated circuits | Oct 29, 1998 | Issued |
Array
(
[id] => 4358894
[patent_doc_number] => 06255215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Semiconductor device having silicide layers formed using a collimated metal layer'
[patent_app_type] => 1
[patent_app_number] => 9/175652
[patent_app_country] => US
[patent_app_date] => 1998-10-20
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[pdf_file] => patents/06/255/06255215.pdf
[firstpage_image] =>[orig_patent_app_number] => 175652
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175652 | Semiconductor device having silicide layers formed using a collimated metal layer | Oct 19, 1998 | Issued |
Array
(
[id] => 1594424
[patent_doc_number] => 06383883
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Method of reducing junction capacitance of source/drain region'
[patent_app_type] => B1
[patent_app_number] => 09/173831
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[patent_app_date] => 1998-10-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/173831 | Method of reducing junction capacitance of source/drain region | Oct 15, 1998 | Issued |
Array
(
[id] => 4380545
[patent_doc_number] => 06261865
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Multi chip semiconductor package and method of construction'
[patent_app_type] => 1
[patent_app_number] => 9/167258
[patent_app_country] => US
[patent_app_date] => 1998-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/261/06261865.pdf
[firstpage_image] =>[orig_patent_app_number] => 167258
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167258 | Multi chip semiconductor package and method of construction | Oct 5, 1998 | Issued |
Array
(
[id] => 4312978
[patent_doc_number] => 06242347
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for cleaning a process chamber'
[patent_app_type] => 1
[patent_app_number] => 9/163711
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/242/06242347.pdf
[firstpage_image] =>[orig_patent_app_number] => 163711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163711 | Method for cleaning a process chamber | Sep 29, 1998 | Issued |
Array
(
[id] => 4237003
[patent_doc_number] => 06090666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method for fabricating semiconductor nanocrystal and semiconductor memory device using the semiconductor nanocrystal'
[patent_app_type] => 1
[patent_app_number] => 9/163552
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[firstpage_image] =>[orig_patent_app_number] => 163552
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163552 | Method for fabricating semiconductor nanocrystal and semiconductor memory device using the semiconductor nanocrystal | Sep 29, 1998 | Issued |
Array
(
[id] => 4169161
[patent_doc_number] => 06140191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions'
[patent_app_type] => 1
[patent_app_number] => 9/157973
[patent_app_country] => US
[patent_app_date] => 1998-09-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157973 | Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions | Sep 20, 1998 | Issued |
Array
(
[id] => 4293069
[patent_doc_number] => 06197602
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[patent_issue_date] => 2001-03-06
[patent_title] => 'Burn-in method for microwave semiconductor transistor'
[patent_app_type] => 1
[patent_app_number] => 9/148793
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[pdf_file] => patents/06/197/06197602.pdf
[firstpage_image] =>[orig_patent_app_number] => 148793
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148793 | Burn-in method for microwave semiconductor transistor | Sep 3, 1998 | Issued |
Array
(
[id] => 4287133
[patent_doc_number] => 06268282
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[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks'
[patent_app_type] => 1
[patent_app_number] => 9/146841
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146841 | Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks | Sep 2, 1998 | Issued |
Array
(
[id] => 4275714
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Array
(
[id] => 4407822
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[patent_title] => 'Yield based, in-line defect sampling method'
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Array
(
[id] => 4359174
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Array
(
[id] => 4358552
[patent_doc_number] => 06168977
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[patent_issue_date] => 2001-01-02
[patent_title] => 'Method of manufacturing a semiconductor device having conductive patterns'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135553 | Method of manufacturing a semiconductor device having conductive patterns | Aug 17, 1998 | Issued |
Array
(
[id] => 4294042
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132732 | Multiple finger polysilicon gate structure and method of making | Aug 11, 1998 | Issued |
Array
(
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Array
(
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Array
(
[id] => 4130702
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[firstpage_image] =>[orig_patent_app_number] => 124876
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124876 | Method of testing a ball grid array IC | Jul 29, 1998 | Issued |