
Kourtney Salzman Carlson
Examiner (ID: 7621, Phone: (571)270-5117 , Office: P/1756 )
| Most Active Art Unit | 1721 |
| Art Unit(s) | 1756, 1724, 1721, 1795 |
| Total Applications | 707 |
| Issued Applications | 283 |
| Pending Applications | 71 |
| Abandoned Applications | 360 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20450090
[patent_doc_number] => 20260006819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-01
[patent_title] => METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 19/320623
[patent_app_country] => US
[patent_app_date] => 2025-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19320623
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/320623 | Method to produce a 3D multilayer semiconductor device and structure | Sep 4, 2025 | Issued |
Array
(
[id] => 20748303
[patent_doc_number] => 12648243
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Biasing and readout methods for high-speed resistive gate sensor
[patent_app_type] => utility
[patent_app_number] => 18/809802
[patent_app_country] => US
[patent_app_date] => 2024-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6810
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809802
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/809802 | Biasing and readout methods for high-speed resistive gate sensor | Aug 19, 2024 | Issued |
Array
(
[id] => 20260555
[patent_doc_number] => 12432926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-30
[patent_title] => Method to produce a 3D multilayer semiconductor device and structure
[patent_app_type] => utility
[patent_app_number] => 18/793939
[patent_app_country] => US
[patent_app_date] => 2024-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 85
[patent_figures_cnt] => 172
[patent_no_of_words] => 29990
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793939
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/793939 | Method to produce a 3D multilayer semiconductor device and structure | Aug 4, 2024 | Issued |
Array
(
[id] => 20476099
[patent_doc_number] => 20260018320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-15
[patent_title] => THIN FILM RESISTOR WITH VIABAR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/772320
[patent_app_country] => US
[patent_app_date] => 2024-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772320
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/772320 | Thin film resistor with viabar structure | Jul 14, 2024 | Issued |
Array
(
[id] => 19935021
[patent_doc_number] => 12308229
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Method for making memory device including a superlattice gettering layer
[patent_app_type] => utility
[patent_app_number] => 18/761691
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761691
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761691 | Method for making memory device including a superlattice gettering layer | Jul 1, 2024 | Issued |
Array
(
[id] => 20692091
[patent_doc_number] => 12622267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Array of heat-sinked power semiconductors
[patent_app_type] => utility
[patent_app_number] => 18/745743
[patent_app_country] => US
[patent_app_date] => 2024-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745743
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/745743 | Array of heat-sinked power semiconductors | Jun 16, 2024 | Issued |
Array
(
[id] => 19486668
[patent_doc_number] => 20240334710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/740496
[patent_app_country] => US
[patent_app_date] => 2024-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740496
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/740496 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jun 10, 2024 | Pending |
Array
(
[id] => 19728769
[patent_doc_number] => 20250031520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => DISPLAY DEVICE AND A METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/732807
[patent_app_country] => US
[patent_app_date] => 2024-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13384
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732807
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/732807 | DISPLAY DEVICE AND A METHOD FOR MANUFACTURING THE SAME | Jun 3, 2024 | Pending |
Array
(
[id] => 19604984
[patent_doc_number] => 20240395864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/733674
[patent_app_country] => US
[patent_app_date] => 2024-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5843
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733674
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/733674 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Jun 3, 2024 | Pending |
Array
(
[id] => 20396907
[patent_doc_number] => 20250372382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => Treatments for Improving Fracture Strength for Semiconductor Workpiece
[patent_app_type] => utility
[patent_app_number] => 18/680764
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9007
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680764
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/680764 | Treatments for Improving Fracture Strength for Semiconductor Workpiece | May 30, 2024 | Pending |
Array
(
[id] => 19712725
[patent_doc_number] => 20250022867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/677353
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10516
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677353
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/677353 | DISPLAY APPARATUS | May 28, 2024 | Pending |
Array
(
[id] => 19452999
[patent_doc_number] => 20240313129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SCHOTTKY BARRIER DIODE
[patent_app_type] => utility
[patent_app_number] => 18/676077
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676077
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/676077 | SCHOTTKY BARRIER DIODE | May 27, 2024 | Pending |
Array
(
[id] => 20381816
[patent_doc_number] => 20250364309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => ISOLATION STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING
[patent_app_type] => utility
[patent_app_number] => 18/673546
[patent_app_country] => US
[patent_app_date] => 2024-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8138
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673546
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/673546 | ISOLATION STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING | May 23, 2024 | Pending |
Array
(
[id] => 19452726
[patent_doc_number] => 20240312856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => ELECTRONIC COMPONENT PACKAGE, CIRCUIT MODULE AND METHOD FOR PRODUCING ELECTRONIC COMPONENT PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/674230
[patent_app_country] => US
[patent_app_date] => 2024-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4928
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674230
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/674230 | ELECTRONIC COMPONENT PACKAGE, CIRCUIT MODULE AND METHOD FOR PRODUCING ELECTRONIC COMPONENT PACKAGE | May 23, 2024 | Pending |
Array
(
[id] => 19589614
[patent_doc_number] => 20240387171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => STRUCTURE OF HIGH-RESISTIVITY SILICON-ON-INSULATOR EMBEDDED WITH CHARGE CAPTURE LAYER AND MANUFACTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/660322
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3288
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660322
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/660322 | STRUCTURE OF HIGH-RESISTIVITY SILICON-ON-INSULATOR EMBEDDED WITH CHARGE CAPTURE LAYER AND MANUFACTURE THEREOF | May 9, 2024 | Pending |
Array
(
[id] => 20324798
[patent_doc_number] => 20250336886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => INTEGRATED CIRCUIT (IC) WITH EXPOSED ACTIVE CIRCUITRY
[patent_app_type] => utility
[patent_app_number] => 18/651057
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651057
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651057 | INTEGRATED CIRCUIT (IC) WITH EXPOSED ACTIVE CIRCUITRY | Apr 29, 2024 | Pending |
Array
(
[id] => 20324713
[patent_doc_number] => 20250336801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => c/o onsemi
[patent_app_type] => utility
[patent_app_number] => 18/649686
[patent_app_country] => US
[patent_app_date] => 2024-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2237
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/649686 | c/o onsemi | Apr 28, 2024 | Pending |
Array
(
[id] => 19560211
[patent_doc_number] => 20240372003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING A FIELD-EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 18/649886
[patent_app_country] => US
[patent_app_date] => 2024-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3685
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649886
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/649886 | FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING A FIELD-EFFECT TRANSISTOR | Apr 28, 2024 | Pending |
Array
(
[id] => 19823337
[patent_doc_number] => 20250081544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => WIDE-BAND-GAP DIODE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/644400
[patent_app_country] => US
[patent_app_date] => 2024-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4226
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644400
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/644400 | WIDE-BAND-GAP DIODE AND MANUFACTURING METHOD THEREOF | Apr 23, 2024 | Pending |
Array
(
[id] => 19646646
[patent_doc_number] => 20240421166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/641596
[patent_app_country] => US
[patent_app_date] => 2024-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12956
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641596
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/641596 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Apr 21, 2024 | Pending |