Search

Kretelia Graham

Examiner (ID: 7064)

Most Active Art Unit
2827
Art Unit(s)
2825, 2615, 2817, 2827
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8962177 [patent_doc_number] => 20130201779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM' [patent_app_type] => utility [patent_app_number] => 13/719610 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3513 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719610
Electronic apparatus, DRAM controller, and DRAM Dec 18, 2012 Issued
Array ( [id] => 10624181 [patent_doc_number] => 09343129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Magnetic memory' [patent_app_type] => utility [patent_app_number] => 13/719896 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 9707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719896 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719896
Magnetic memory Dec 18, 2012 Issued
Array ( [id] => 10576804 [patent_doc_number] => 09299454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'CAS latency setting circuit and semiconductor memory apparatus including the same' [patent_app_type] => utility [patent_app_number] => 13/720204 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2961 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720204
CAS latency setting circuit and semiconductor memory apparatus including the same Dec 18, 2012 Issued
Array ( [id] => 9203991 [patent_doc_number] => 20140003168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/719096 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6659 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719096
Semiconductor integrated circuit with stack package structure Dec 17, 2012 Issued
Array ( [id] => 9329301 [patent_doc_number] => 20140056083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/719196 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9060 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719196
Semiconductor memory device using a current mirror Dec 17, 2012 Issued
Array ( [id] => 10893946 [patent_doc_number] => 08917572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Semiconductor memory device and method of testing the same' [patent_app_type] => utility [patent_app_number] => 13/719066 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5521 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719066 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719066
Semiconductor memory device and method of testing the same Dec 17, 2012 Issued
Array ( [id] => 10131777 [patent_doc_number] => 09165618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Semiconductor memory device for conducting monitoring operation to verify read and write operations' [patent_app_type] => utility [patent_app_number] => 13/719018 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4815 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719018
Semiconductor memory device for conducting monitoring operation to verify read and write operations Dec 17, 2012 Issued
Array ( [id] => 11200846 [patent_doc_number] => 09431064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Memory circuit and cache circuit configuration' [patent_app_type] => utility [patent_app_number] => 13/667924 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/667924
Memory circuit and cache circuit configuration Nov 1, 2012 Issued
Array ( [id] => 8813318 [patent_doc_number] => 20130114363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'MULTI-MODAL MEMORY INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/667520 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4585 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/667520
Multi-modal memory interface Nov 1, 2012 Issued
Array ( [id] => 9461860 [patent_doc_number] => 20140126286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS' [patent_app_type] => utility [patent_app_number] => 13/668160 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16043 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13668160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/668160
Single-level cell endurance improvement with pre-defined blocks Nov 1, 2012 Issued
Array ( [id] => 9447978 [patent_doc_number] => 20140119147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEGMENTED MEMORY HAVING POWER-SAVING MODE' [patent_app_type] => utility [patent_app_number] => 13/664772 [patent_app_country] => US [patent_app_date] => 2012-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4198 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/664772
Segmented memory having power-saving mode Oct 30, 2012 Issued
Array ( [id] => 9884370 [patent_doc_number] => 08971147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Control gate word line driver circuit for multigate memory' [patent_app_type] => utility [patent_app_number] => 13/663636 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4806 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663636
Control gate word line driver circuit for multigate memory Oct 29, 2012 Issued
Array ( [id] => 9447977 [patent_doc_number] => 20140119146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'Clock Gated Storage Array' [patent_app_type] => utility [patent_app_number] => 13/663946 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2786 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663946 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663946
Clock Gated Storage Array Oct 29, 2012 Abandoned
Array ( [id] => 8864740 [patent_doc_number] => 20130148444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'DATA READING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/663952 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663952
Data reading device Oct 29, 2012 Issued
Array ( [id] => 9002053 [patent_doc_number] => 20130223178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS' [patent_app_type] => utility [patent_app_number] => 13/663042 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10127 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663042 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663042
Global reset with replica for pulse latch pre-decoders Oct 28, 2012 Issued
Array ( [id] => 9484792 [patent_doc_number] => 08730750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Memory device with control circuitry for generating a reset signal in read and write modes of operation' [patent_app_type] => utility [patent_app_number] => 13/662504 [patent_app_country] => US [patent_app_date] => 2012-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6409 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662504
Memory device with control circuitry for generating a reset signal in read and write modes of operation Oct 27, 2012 Issued
Array ( [id] => 10053272 [patent_doc_number] => 09093152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multiple data line memory and methods' [patent_app_type] => utility [patent_app_number] => 13/661498 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9134 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661498 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661498
Multiple data line memory and methods Oct 25, 2012 Issued
Array ( [id] => 8731855 [patent_doc_number] => 20130077424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA' [patent_app_type] => utility [patent_app_number] => 13/625461 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3147 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625461
SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA Sep 23, 2012 Abandoned
Array ( [id] => 10833087 [patent_doc_number] => 08861266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Planar phase-change memory cell with parallel electrical paths' [patent_app_type] => utility [patent_app_number] => 13/619473 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 8023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619473 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619473
Planar phase-change memory cell with parallel electrical paths Sep 13, 2012 Issued
Array ( [id] => 8584643 [patent_doc_number] => 20130003464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CIRCUITS, SYSTEMS, AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/610512 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3435 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610512
Circuits, systems, and methods for driving high and low voltages on bit lines in non-volatile memory Sep 10, 2012 Issued
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