
Kretelia Graham
Examiner (ID: 7064)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2615, 2817, 2827 |
| Total Applications | 682 |
| Issued Applications | 565 |
| Pending Applications | 4 |
| Abandoned Applications | 116 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8962177
[patent_doc_number] => 20130201779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-08
[patent_title] => 'ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM'
[patent_app_type] => utility
[patent_app_number] => 13/719610
[patent_app_country] => US
[patent_app_date] => 2012-12-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719610 | Electronic apparatus, DRAM controller, and DRAM | Dec 18, 2012 | Issued |
Array
(
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[patent_doc_number] => 09343129
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[patent_kind] => B2
[patent_issue_date] => 2016-05-17
[patent_title] => 'Magnetic memory'
[patent_app_type] => utility
[patent_app_number] => 13/719896
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Array
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[patent_issue_date] => 2016-03-29
[patent_title] => 'CAS latency setting circuit and semiconductor memory apparatus including the same'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2014-01-02
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
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[patent_app_date] => 2012-12-18
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Array
(
[id] => 9329301
[patent_doc_number] => 20140056083
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[patent_issue_date] => 2014-02-27
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719196 | Semiconductor memory device using a current mirror | Dec 17, 2012 | Issued |
Array
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[patent_issue_date] => 2014-12-23
[patent_title] => 'Semiconductor memory device and method of testing the same'
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Array
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[patent_title] => 'Semiconductor memory device for conducting monitoring operation to verify read and write operations'
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Array
(
[id] => 11200846
[patent_doc_number] => 09431064
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[patent_title] => 'Memory circuit and cache circuit configuration'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667924 | Memory circuit and cache circuit configuration | Nov 1, 2012 | Issued |
Array
(
[id] => 8813318
[patent_doc_number] => 20130114363
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[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'MULTI-MODAL MEMORY INTERFACE'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667520 | Multi-modal memory interface | Nov 1, 2012 | Issued |
Array
(
[id] => 9461860
[patent_doc_number] => 20140126286
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[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS'
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[patent_app_number] => 13/668160
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/668160 | Single-level cell endurance improvement with pre-defined blocks | Nov 1, 2012 | Issued |
Array
(
[id] => 9447978
[patent_doc_number] => 20140119147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-01
[patent_title] => 'SEGMENTED MEMORY HAVING POWER-SAVING MODE'
[patent_app_type] => utility
[patent_app_number] => 13/664772
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/664772 | Segmented memory having power-saving mode | Oct 30, 2012 | Issued |
Array
(
[id] => 9884370
[patent_doc_number] => 08971147
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[patent_title] => 'Control gate word line driver circuit for multigate memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/663636 | Control gate word line driver circuit for multigate memory | Oct 29, 2012 | Issued |
Array
(
[id] => 9447977
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/663946 | Clock Gated Storage Array | Oct 29, 2012 | Abandoned |
Array
(
[id] => 8864740
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/663952 | Data reading device | Oct 29, 2012 | Issued |
Array
(
[id] => 9002053
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[patent_title] => 'GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/663042 | Global reset with replica for pulse latch pre-decoders | Oct 28, 2012 | Issued |
Array
(
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Array
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Array
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Array
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