Search

Kretelia Graham

Examiner (ID: 11675, Phone: (571)272-5055 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2817, 2827, 2615, 2825
Total Applications
682
Issued Applications
562
Pending Applications
12
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9484792 [patent_doc_number] => 08730750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Memory device with control circuitry for generating a reset signal in read and write modes of operation' [patent_app_type] => utility [patent_app_number] => 13/662504 [patent_app_country] => US [patent_app_date] => 2012-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6409 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662504
Memory device with control circuitry for generating a reset signal in read and write modes of operation Oct 27, 2012 Issued
Array ( [id] => 10053272 [patent_doc_number] => 09093152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multiple data line memory and methods' [patent_app_type] => utility [patent_app_number] => 13/661498 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9134 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661498 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661498
Multiple data line memory and methods Oct 25, 2012 Issued
Array ( [id] => 8731855 [patent_doc_number] => 20130077424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA' [patent_app_type] => utility [patent_app_number] => 13/625461 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3147 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625461
SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA Sep 23, 2012 Abandoned
Array ( [id] => 10833087 [patent_doc_number] => 08861266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Planar phase-change memory cell with parallel electrical paths' [patent_app_type] => utility [patent_app_number] => 13/619473 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 8023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619473 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619473
Planar phase-change memory cell with parallel electrical paths Sep 13, 2012 Issued
Array ( [id] => 8584643 [patent_doc_number] => 20130003464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CIRCUITS, SYSTEMS, AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/610512 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3435 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610512
Circuits, systems, and methods for driving high and low voltages on bit lines in non-volatile memory Sep 10, 2012 Issued
Array ( [id] => 9356857 [patent_doc_number] => 08675403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Gated diode memory cells' [patent_app_type] => utility [patent_app_number] => 13/571094 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/571094
Gated diode memory cells Aug 8, 2012 Issued
Array ( [id] => 9884357 [patent_doc_number] => 08971134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Memory controller comprising adjustable transmitter impedance' [patent_app_type] => utility [patent_app_number] => 13/561228 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561228
Memory controller comprising adjustable transmitter impedance Jul 29, 2012 Issued
Array ( [id] => 8440838 [patent_doc_number] => 20120257454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION' [patent_app_type] => utility [patent_app_number] => 13/530026 [patent_app_country] => US [patent_app_date] => 2012-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5608 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530026 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/530026
Flash storage device with data integrity protection Jun 20, 2012 Issued
Array ( [id] => 9442516 [patent_doc_number] => 08711638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Using storage cells to perform computation' [patent_app_type] => utility [patent_app_number] => 13/437956 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5379 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437956
Using storage cells to perform computation Apr 2, 2012 Issued
Array ( [id] => 8415784 [patent_doc_number] => 20120243284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'USING STORAGE CELLS TO PERFORM COMPUTATION' [patent_app_type] => utility [patent_app_number] => 13/437955 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5462 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437955
Using storage cells to perform computation Apr 2, 2012 Issued
Array ( [id] => 9356886 [patent_doc_number] => 08675432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Semiconductor device capable of being tested after packaging' [patent_app_type] => utility [patent_app_number] => 13/437282 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3757 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437282
Semiconductor device capable of being tested after packaging Apr 1, 2012 Issued
Array ( [id] => 8288523 [patent_doc_number] => 20120176848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING BIT LINE EQUALIZING SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/429557 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6951 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/429557
Semiconductor memory device and method for generating bit line equalizing signal Mar 25, 2012 Issued
Array ( [id] => 8349184 [patent_doc_number] => 20120210108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/367708 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13367708 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/367708
SEMICONDUCTOR DEVICE Feb 6, 2012 Abandoned
Array ( [id] => 8213819 [patent_doc_number] => 20120131267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/359012 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131267.pdf [firstpage_image] =>[orig_patent_app_number] => 13359012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359012
Memory device distributed controller system Jan 25, 2012 Issued
Array ( [id] => 9075859 [patent_doc_number] => 08553443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Memory device and memory access method' [patent_app_type] => utility [patent_app_number] => 13/357712 [patent_app_country] => US [patent_app_date] => 2012-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7363 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357712 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357712
Memory device and memory access method Jan 24, 2012 Issued
Array ( [id] => 9368937 [patent_doc_number] => 20140078810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'LOADLESS VOLATILE/NON-VOLATILE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/980555 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980555
LOADLESS VOLATILE/NON-VOLATILE MEMORY CELL Jan 18, 2012 Abandoned
Array ( [id] => 8835916 [patent_doc_number] => 08451681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Semiconductor storage device including memory cells each having a variable resistance element' [patent_app_type] => utility [patent_app_number] => 13/309334 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 12059 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/309334
Semiconductor storage device including memory cells each having a variable resistance element Nov 30, 2011 Issued
Array ( [id] => 8039881 [patent_doc_number] => 20120069675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'REDUCING NOISE IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/308976 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069675.pdf [firstpage_image] =>[orig_patent_app_number] => 13308976 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308976
Reducing noise in semiconductor devices Nov 30, 2011 Issued
Array ( [id] => 8039921 [patent_doc_number] => 20120069693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/305064 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9849 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069693.pdf [firstpage_image] =>[orig_patent_app_number] => 13305064 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305064
Dynamic random access memory and boosted voltage producer therefor Nov 27, 2011 Issued
Array ( [id] => 7819821 [patent_doc_number] => 20120066441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/301308 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11556 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066441.pdf [firstpage_image] =>[orig_patent_app_number] => 13301308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301308
Systems and methods for averaging error rates in non-volatile devices and storage systems Nov 20, 2011 Issued
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