Search

Kretelia Graham

Examiner (ID: 7064)

Most Active Art Unit
2827
Art Unit(s)
2825, 2615, 2817, 2827
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9356857 [patent_doc_number] => 08675403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Gated diode memory cells' [patent_app_type] => utility [patent_app_number] => 13/571094 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/571094
Gated diode memory cells Aug 8, 2012 Issued
Array ( [id] => 9884357 [patent_doc_number] => 08971134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Memory controller comprising adjustable transmitter impedance' [patent_app_type] => utility [patent_app_number] => 13/561228 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561228
Memory controller comprising adjustable transmitter impedance Jul 29, 2012 Issued
Array ( [id] => 8440838 [patent_doc_number] => 20120257454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION' [patent_app_type] => utility [patent_app_number] => 13/530026 [patent_app_country] => US [patent_app_date] => 2012-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5608 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530026 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/530026
Flash storage device with data integrity protection Jun 20, 2012 Issued
Array ( [id] => 9442516 [patent_doc_number] => 08711638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Using storage cells to perform computation' [patent_app_type] => utility [patent_app_number] => 13/437956 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5379 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437956
Using storage cells to perform computation Apr 2, 2012 Issued
Array ( [id] => 8415784 [patent_doc_number] => 20120243284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'USING STORAGE CELLS TO PERFORM COMPUTATION' [patent_app_type] => utility [patent_app_number] => 13/437955 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5462 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437955
Using storage cells to perform computation Apr 2, 2012 Issued
Array ( [id] => 9356886 [patent_doc_number] => 08675432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Semiconductor device capable of being tested after packaging' [patent_app_type] => utility [patent_app_number] => 13/437282 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3757 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437282
Semiconductor device capable of being tested after packaging Apr 1, 2012 Issued
Array ( [id] => 8288523 [patent_doc_number] => 20120176848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING BIT LINE EQUALIZING SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/429557 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6951 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/429557
Semiconductor memory device and method for generating bit line equalizing signal Mar 25, 2012 Issued
Array ( [id] => 8349184 [patent_doc_number] => 20120210108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/367708 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13367708 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/367708
SEMICONDUCTOR DEVICE Feb 6, 2012 Abandoned
Array ( [id] => 8213819 [patent_doc_number] => 20120131267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/359012 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131267.pdf [firstpage_image] =>[orig_patent_app_number] => 13359012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359012
Memory device distributed controller system Jan 25, 2012 Issued
Array ( [id] => 9075859 [patent_doc_number] => 08553443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Memory device and memory access method' [patent_app_type] => utility [patent_app_number] => 13/357712 [patent_app_country] => US [patent_app_date] => 2012-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7363 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357712 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357712
Memory device and memory access method Jan 24, 2012 Issued
Array ( [id] => 9368937 [patent_doc_number] => 20140078810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'LOADLESS VOLATILE/NON-VOLATILE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/980555 [patent_app_country] => US [patent_app_date] => 2012-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980555
LOADLESS VOLATILE/NON-VOLATILE MEMORY CELL Jan 18, 2012 Abandoned
Array ( [id] => 8039881 [patent_doc_number] => 20120069675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'REDUCING NOISE IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/308976 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069675.pdf [firstpage_image] =>[orig_patent_app_number] => 13308976 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308976
Reducing noise in semiconductor devices Nov 30, 2011 Issued
Array ( [id] => 8835916 [patent_doc_number] => 08451681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Semiconductor storage device including memory cells each having a variable resistance element' [patent_app_type] => utility [patent_app_number] => 13/309334 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 12059 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/309334
Semiconductor storage device including memory cells each having a variable resistance element Nov 30, 2011 Issued
Array ( [id] => 8039921 [patent_doc_number] => 20120069693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/305064 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9849 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20120069693.pdf [firstpage_image] =>[orig_patent_app_number] => 13305064 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305064
Dynamic random access memory and boosted voltage producer therefor Nov 27, 2011 Issued
Array ( [id] => 7819821 [patent_doc_number] => 20120066441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/301308 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11556 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066441.pdf [firstpage_image] =>[orig_patent_app_number] => 13301308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301308
Systems and methods for averaging error rates in non-volatile devices and storage systems Nov 20, 2011 Issued
Array ( [id] => 7783210 [patent_doc_number] => 20120044766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/285099 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9377 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044766.pdf [firstpage_image] =>[orig_patent_app_number] => 13285099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285099
Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same Oct 30, 2011 Issued
Array ( [id] => 8631361 [patent_doc_number] => 08363445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'One-time programmable memory cell' [patent_app_type] => utility [patent_app_number] => 13/283267 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283267
One-time programmable memory cell Oct 26, 2011 Issued
Array ( [id] => 7774844 [patent_doc_number] => 20120039106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Programmable Memory Cell with Shiftable Threshold Voltage Transistor' [patent_app_type] => utility [patent_app_number] => 13/283418 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4071 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20120039106.pdf [firstpage_image] =>[orig_patent_app_number] => 13283418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283418
Programmable memory cell with shiftable threshold voltage transistor Oct 26, 2011 Issued
Array ( [id] => 7774869 [patent_doc_number] => 20120039123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/279717 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3623 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20120039123.pdf [firstpage_image] =>[orig_patent_app_number] => 13279717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/279717
MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE Oct 23, 2011 Abandoned
Array ( [id] => 7730149 [patent_doc_number] => 20120014185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/240914 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20120014185.pdf [firstpage_image] =>[orig_patent_app_number] => 13240914 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240914
Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory Sep 21, 2011 Issued
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