
Kretelia Graham
Examiner (ID: 7064)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2615, 2817, 2827 |
| Total Applications | 682 |
| Issued Applications | 565 |
| Pending Applications | 4 |
| Abandoned Applications | 116 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9991177
[patent_doc_number] => 09036392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-19
[patent_title] => 'Redundancy circuit for reducing chip area'
[patent_app_type] => utility
[patent_app_number] => 13/207650
[patent_app_country] => US
[patent_app_date] => 2011-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3319
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207650
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/207650 | Redundancy circuit for reducing chip area | Aug 10, 2011 | Issued |
Array
(
[id] => 8415825
[patent_doc_number] => 20120243325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-27
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/206686
[patent_app_country] => US
[patent_app_date] => 2011-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5185
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13206686
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/206686 | SEMICONDUCTOR MEMORY DEVICE | Aug 9, 2011 | Abandoned |
Array
(
[id] => 7774905
[patent_doc_number] => 20120039144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'Semiconductor device with shortened data read time'
[patent_app_type] => utility
[patent_app_number] => 13/137388
[patent_app_country] => US
[patent_app_date] => 2011-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6079
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20120039144.pdf
[firstpage_image] =>[orig_patent_app_number] => 13137388
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137388 | Semiconductor device with shortened data read time | Aug 9, 2011 | Abandoned |
Array
(
[id] => 9846031
[patent_doc_number] => 08947959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-03
[patent_title] => 'Memory device and compressive test method for the same'
[patent_app_type] => utility
[patent_app_number] => 13/206180
[patent_app_country] => US
[patent_app_date] => 2011-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10892
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13206180
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/206180 | Memory device and compressive test method for the same | Aug 8, 2011 | Issued |
Array
(
[id] => 11910996
[patent_doc_number] => 09779814
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-03
[patent_title] => 'Non-volatile static random access memory devices and methods of operations'
[patent_app_type] => utility
[patent_app_number] => 13/206270
[patent_app_country] => US
[patent_app_date] => 2011-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5880
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13206270
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/206270 | Non-volatile static random access memory devices and methods of operations | Aug 8, 2011 | Issued |
Array
(
[id] => 9234326
[patent_doc_number] => 08599635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-03
[patent_title] => 'Fuse circuit and semiconductor memory device including the same'
[patent_app_type] => utility
[patent_app_number] => 13/205966
[patent_app_country] => US
[patent_app_date] => 2011-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 13571
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13205966
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/205966 | Fuse circuit and semiconductor memory device including the same | Aug 8, 2011 | Issued |
Array
(
[id] => 11701775
[patent_doc_number] => 09691700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Semiconductor device including first and second dummy wirings'
[patent_app_type] => utility
[patent_app_number] => 13/137252
[patent_app_country] => US
[patent_app_date] => 2011-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7634
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137252
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137252 | Semiconductor device including first and second dummy wirings | Jul 31, 2011 | Issued |
Array
(
[id] => 7585569
[patent_doc_number] => 20110280079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-17
[patent_title] => 'NAND FLASH MEMORY PROGRAMMING'
[patent_app_type] => utility
[patent_app_number] => 13/189678
[patent_app_country] => US
[patent_app_date] => 2011-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0280/20110280079.pdf
[firstpage_image] =>[orig_patent_app_number] => 13189678
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/189678 | NAND flash memory programming | Jul 24, 2011 | Issued |
Array
(
[id] => 7752904
[patent_doc_number] => 20120026813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'Semiconductor device changing an active time-out time interval'
[patent_app_type] => utility
[patent_app_number] => 13/137030
[patent_app_country] => US
[patent_app_date] => 2011-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8736
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20120026813.pdf
[firstpage_image] =>[orig_patent_app_number] => 13137030
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137030 | Semiconductor device changing an active time-out time interval | Jul 14, 2011 | Issued |
Array
(
[id] => 7572232
[patent_doc_number] => 20110267888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-03
[patent_title] => 'Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory'
[patent_app_type] => utility
[patent_app_number] => 13/181750
[patent_app_country] => US
[patent_app_date] => 2011-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8180
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20110267888.pdf
[firstpage_image] =>[orig_patent_app_number] => 13181750
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/181750 | Controlling select gate voltage during erase to improve endurance in non volatile memory | Jul 12, 2011 | Issued |
Array
(
[id] => 8428562
[patent_doc_number] => 20120250438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-04
[patent_title] => 'Dynamic random access memory address line test technique'
[patent_app_type] => utility
[patent_app_number] => 13/135374
[patent_app_country] => US
[patent_app_date] => 2011-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1810
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13135374
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/135374 | Dynamic random access memory address line test technique | Jun 30, 2011 | Issued |
Array
(
[id] => 11246223
[patent_doc_number] => 09472268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-18
[patent_title] => 'SRAM with buffered-read bit cells and its testing'
[patent_app_type] => utility
[patent_app_number] => 13/135198
[patent_app_country] => US
[patent_app_date] => 2011-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 4749
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13135198
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/135198 | SRAM with buffered-read bit cells and its testing | Jun 26, 2011 | Issued |
Array
(
[id] => 7485197
[patent_doc_number] => 20110235446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'WRITE STROBE GENERATION FOR A MEMORY INTERFACE CONTROLLER'
[patent_app_type] => utility
[patent_app_number] => 13/156134
[patent_app_country] => US
[patent_app_date] => 2011-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4605
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20110235446.pdf
[firstpage_image] =>[orig_patent_app_number] => 13156134
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/156134 | Write strobe generation for a memory interface controller | Jun 7, 2011 | Issued |
Array
(
[id] => 8330117
[patent_doc_number] => 08238188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Semiconductor memory device changing refresh interval depending on temperature'
[patent_app_type] => utility
[patent_app_number] => 13/026987
[patent_app_country] => US
[patent_app_date] => 2011-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5877
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026987
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/026987 | Semiconductor memory device changing refresh interval depending on temperature | Feb 13, 2011 | Issued |
Array
(
[id] => 6210859
[patent_doc_number] => 20110134706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-09
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/026649
[patent_app_country] => US
[patent_app_date] => 2011-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 17424
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20110134706.pdf
[firstpage_image] =>[orig_patent_app_number] => 13026649
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/026649 | Semiconductor memory device having multiple ports | Feb 13, 2011 | Issued |
Array
(
[id] => 8798339
[patent_doc_number] => 08437217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-07
[patent_title] => 'Storing operational information in an array of memory cells'
[patent_app_type] => utility
[patent_app_number] => 13/012020
[patent_app_country] => US
[patent_app_date] => 2011-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 8183
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13012020
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/012020 | Storing operational information in an array of memory cells | Jan 23, 2011 | Issued |
Array
(
[id] => 7485044
[patent_doc_number] => 20110235393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'Nonvolatile storage device'
[patent_app_type] => utility
[patent_app_number] => 12/929360
[patent_app_country] => US
[patent_app_date] => 2011-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 11983
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20110235393.pdf
[firstpage_image] =>[orig_patent_app_number] => 12929360
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/929360 | Nonvolatile storage device having a plurality of plate electrodes | Jan 18, 2011 | Issued |
Array
(
[id] => 6053806
[patent_doc_number] => 20110110166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-12
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/008423
[patent_app_country] => US
[patent_app_date] => 2011-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 20870
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20110110166.pdf
[firstpage_image] =>[orig_patent_app_number] => 13008423
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/008423 | SEMICONDUCTOR DEVICE | Jan 17, 2011 | Abandoned |
Array
(
[id] => 6044859
[patent_doc_number] => 20110205826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'Storage control device, storage device and storage device system'
[patent_app_type] => utility
[patent_app_number] => 12/929272
[patent_app_country] => US
[patent_app_date] => 2011-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 15947
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20110205826.pdf
[firstpage_image] =>[orig_patent_app_number] => 12929272
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/929272 | Storage control device controlling refresh frequency based on temperature | Jan 11, 2011 | Issued |
Array
(
[id] => 8276537
[patent_doc_number] => 20120170390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'Read stability of a semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 12/929138
[patent_app_country] => US
[patent_app_date] => 2011-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7369
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12929138
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/929138 | Improving read stability of a semiconductor memory | Jan 2, 2011 | Issued |