Kretelia Graham

Array ( [id] => 4598616 [patent_doc_number] => 07983101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Circuit for generating data strobe signal in DDR memory device and method therefor' [patent_app_type] => utility [patent_app_number] => 12/727185 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5151 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983101.pdf [firstpage_image] =>[orig_patent_app_number] => 12727185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4605598 [patent_doc_number] => 07986581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Semiconductor memory device including reset control circuit' [patent_app_type] => utility [patent_app_number] => 12/715146 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1920 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986581.pdf [firstpage_image] =>[orig_patent_app_number] => 12715146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8934101 [patent_doc_number] => 08493811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Memory having asynchronous read with fast read output' [patent_app_type] => utility [patent_app_number] => 12/703446 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8295732 [patent_doc_number] => 08223529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Resistive memory devices, memory systems and methods of controlling input and output operations of the same' [patent_app_type] => utility [patent_app_number] => 12/703354 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9008 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6464678 [patent_doc_number] => 20100284226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/702480 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5606 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20100284226.pdf [firstpage_image] =>[orig_patent_app_number] => 12702480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6163432 [patent_doc_number] => 20110194333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'System and Method to Select a Reference Cell' [patent_app_type] => utility [patent_app_number] => 12/702486 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11322 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194333.pdf [firstpage_image] =>[orig_patent_app_number] => 12702486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6520301 [patent_doc_number] => 20100220525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND ERASE AND READ METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/702634 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6798 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220525.pdf [firstpage_image] =>[orig_patent_app_number] => 12702634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6520216 [patent_doc_number] => 20100220517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/702724 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 38508 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220517.pdf [firstpage_image] =>[orig_patent_app_number] => 12702724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6163466 [patent_doc_number] => 20110194362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/702594 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194362.pdf [firstpage_image] =>[orig_patent_app_number] => 12702594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6163455 [patent_doc_number] => 20110194352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'PROGRAMMING METHODS AND MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/702948 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5109 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194352.pdf [firstpage_image] =>[orig_patent_app_number] => 12702948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9256054 [patent_doc_number] => 08619482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-31 [patent_title] => 'Programmable precharge circuitry' [patent_app_type] => utility [patent_app_number] => 12/702206 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7711 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12702206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6163458 [patent_doc_number] => 20110194355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'VERIFY WHILE WRITE SCHEME FOR NON-VOLATILE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/702258 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5905 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194355.pdf [firstpage_image] =>[orig_patent_app_number] => 12702258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6508061 [patent_doc_number] => 20100202182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/700882 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7573 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202182.pdf [firstpage_image] =>[orig_patent_app_number] => 12700882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6484030 [patent_doc_number] => 20100208532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'MEMORY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/701144 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7457 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20100208532.pdf [firstpage_image] =>[orig_patent_app_number] => 12701144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8922453 [patent_doc_number] => 08488396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Dual rail static random access memory' [patent_app_type] => utility [patent_app_number] => 12/700034 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3152 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6289540 [patent_doc_number] => 20100238705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/698720 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20100238705.pdf [firstpage_image] =>[orig_patent_app_number] => 12698720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8631386 [patent_doc_number] => 08363469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'All-NMOS 4-transistor non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 12/698318 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8084615 [patent_doc_number] => 08149637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Semiconductor device capable of being tested after packaging' [patent_app_type] => utility [patent_app_number] => 12/698672 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3739 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/149/08149637.pdf [firstpage_image] =>[orig_patent_app_number] => 12698672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6316530 [patent_doc_number] => 20100195396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/698576 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9739 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195396.pdf [firstpage_image] =>[orig_patent_app_number] => 12698576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6276765 [patent_doc_number] => 20100118633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY SENSE AMPLIFIERS AND METHODS OF UTILIZING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/687971 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9422 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118633.pdf [firstpage_image] =>[orig_patent_app_number] => 12687971 [rel_patent_id] =>[rel_patent_doc_number] =>)