Search

Kretelia Graham

Examiner (ID: 7064)

Most Active Art Unit
2827
Art Unit(s)
2825, 2615, 2817, 2827
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6445023 [patent_doc_number] => 20100188912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA' [patent_app_type] => utility [patent_app_number] => 12/685854 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3267 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20100188912.pdf [firstpage_image] =>[orig_patent_app_number] => 12685854 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685854
Semiconductor memory circuit and control method for reading data Jan 11, 2010 Issued
Array ( [id] => 6390874 [patent_doc_number] => 20100177567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH CAN ELECTRICALLY REWRITE DATA AND SYSTEM THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/685982 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5775 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20100177567.pdf [firstpage_image] =>[orig_patent_app_number] => 12685982 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685982
Nonvolatile semiconductor memory device which can electrically rewrite data and system therefor Jan 11, 2010 Issued
Array ( [id] => 6508368 [patent_doc_number] => 20100202211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/686058 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202211.pdf [firstpage_image] =>[orig_patent_app_number] => 12686058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/686058
NONVOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME Jan 11, 2010 Abandoned
Array ( [id] => 8365091 [patent_doc_number] => 08254162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method and system for providing magnetic tunneling junctions usable in spin transfer torque magnetic memories' [patent_app_type] => utility [patent_app_number] => 12/685418 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12685418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685418
Method and system for providing magnetic tunneling junctions usable in spin transfer torque magnetic memories Jan 10, 2010 Issued
Array ( [id] => 6331926 [patent_doc_number] => 20100246309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/684998 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1806 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246309.pdf [firstpage_image] =>[orig_patent_app_number] => 12684998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684998
SEMICONDUCTOR MEMORY Jan 10, 2010 Abandoned
Array ( [id] => 6390901 [patent_doc_number] => 20100177573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 12/684674 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6515 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20100177573.pdf [firstpage_image] =>[orig_patent_app_number] => 12684674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684674
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVING METHOD Jan 7, 2010 Abandoned
Array ( [id] => 4640761 [patent_doc_number] => 08018791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Circuit, system and method for controlling read latency' [patent_app_type] => utility [patent_app_number] => 12/683309 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7329 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018791.pdf [firstpage_image] =>[orig_patent_app_number] => 12683309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/683309
Circuit, system and method for controlling read latency Jan 5, 2010 Issued
Array ( [id] => 6384797 [patent_doc_number] => 20100302826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'CAM CELL CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/650689 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2308 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302826.pdf [firstpage_image] =>[orig_patent_app_number] => 12650689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650689
CAM CELL CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME Dec 30, 2009 Abandoned
Array ( [id] => 6385202 [patent_doc_number] => 20100302881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/650639 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3670 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302881.pdf [firstpage_image] =>[orig_patent_app_number] => 12650639 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650639
Voltage generation circuit and nonvolatile memory device using the same Dec 30, 2009 Issued
Array ( [id] => 6627937 [patent_doc_number] => 20100226171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/650613 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20100226171.pdf [firstpage_image] =>[orig_patent_app_number] => 12650613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650613
METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE Dec 30, 2009 Abandoned
Array ( [id] => 6384812 [patent_doc_number] => 20100302830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/650091 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302830.pdf [firstpage_image] =>[orig_patent_app_number] => 12650091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650091
SEMICONDUCTOR MEMORY DEVICE Dec 29, 2009 Abandoned
Array ( [id] => 8922461 [patent_doc_number] => 08488404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Counter control signal generator and refresh circuit' [patent_app_type] => utility [patent_app_number] => 12/649459 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2762 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12649459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649459
Counter control signal generator and refresh circuit Dec 29, 2009 Issued
Array ( [id] => 6140516 [patent_doc_number] => 20110128795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 12/649393 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5947 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128795.pdf [firstpage_image] =>[orig_patent_app_number] => 12649393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649393
SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER Dec 29, 2009 Abandoned
Array ( [id] => 9390835 [patent_doc_number] => 08687447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Semiconductor memory apparatus and test method using the same' [patent_app_type] => utility [patent_app_number] => 12/650491 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4158 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650491
Semiconductor memory apparatus and test method using the same Dec 29, 2009 Issued
Array ( [id] => 6157425 [patent_doc_number] => 20110158019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/649379 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20110158019.pdf [firstpage_image] =>[orig_patent_app_number] => 12649379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649379
Semiconductor device having bit line equalization using low voltage and a method thereof Dec 29, 2009 Issued
Array ( [id] => 6140514 [patent_doc_number] => 20110128794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'APPARATUS AND METHOD FOR CONTROLLING OPERATION TIMING IN SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/649021 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128794.pdf [firstpage_image] =>[orig_patent_app_number] => 12649021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649021
APPARATUS AND METHOD FOR CONTROLLING OPERATION TIMING IN SEMICONDUCTOR MEMORY DEVICE Dec 28, 2009 Abandoned
Array ( [id] => 5942545 [patent_doc_number] => 20110103165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'SELF-REFRESH TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/649033 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2811 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20110103165.pdf [firstpage_image] =>[orig_patent_app_number] => 12649033 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649033
Self-refresh test circuit of semiconductor memory apparatus Dec 28, 2009 Issued
Array ( [id] => 9924685 [patent_doc_number] => 08982659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Bitline floating during non-access mode for memory arrays' [patent_app_type] => utility [patent_app_number] => 12/645623 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645623
Bitline floating during non-access mode for memory arrays Dec 22, 2009 Issued
Array ( [id] => 6267308 [patent_doc_number] => 20100254187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'MEMORY SYSTEM AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/644685 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20100254187.pdf [firstpage_image] =>[orig_patent_app_number] => 12644685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644685
Memory system with potential rank correction capability Dec 21, 2009 Issued
Array ( [id] => 5966918 [patent_doc_number] => 20110149673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Three State Word Line Driver ForA DRAM Memory Device' [patent_app_type] => utility [patent_app_number] => 12/645321 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3846 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149673.pdf [firstpage_image] =>[orig_patent_app_number] => 12645321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645321
Three state word line driver for a DRAM memory device Dec 21, 2009 Issued
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