
Kretelia Graham
Examiner (ID: 19041, Phone: (571)272-5055 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2827, 2615, 2817 |
| Total Applications | 683 |
| Issued Applications | 562 |
| Pending Applications | 12 |
| Abandoned Applications | 115 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18639282
[patent_doc_number] => 11763898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-19
[patent_title] => Value-voltage-distirubution-intersection-based read disturb information determination system
[patent_app_type] => utility
[patent_app_number] => 17/581879
[patent_app_country] => US
[patent_app_date] => 2022-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 23359
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581879
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/581879 | Value-voltage-distirubution-intersection-based read disturb information determination system | Jan 21, 2022 | Issued |
Array
(
[id] => 18243541
[patent_doc_number] => 20230075852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/579646
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10315
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579646
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579646 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF | Jan 19, 2022 | Pending |
Array
(
[id] => 17779861
[patent_doc_number] => 20220246211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => DEVICE COMPRISING A NON-VOLATILE MEMORY CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/648449
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4329
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648449
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648449 | Buffer memory adapted to implment calculations having operands as data | Jan 19, 2022 | Issued |
Array
(
[id] => 18097063
[patent_doc_number] => 20220415404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => NONVOLATILE MEMORY DEVICES HAVING ADAPTIVE WRITE/READ CONTROL TO IMPROVE READ RELIABILITY AND METHODS OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/579902
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9470
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579902
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579902 | Nonvolatile memory devices having adaptive write/read control to improve read reliability and methods of operating the same | Jan 19, 2022 | Issued |
Array
(
[id] => 18403717
[patent_doc_number] => 11665877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-05-30
[patent_title] => Stacked FET SRAM design
[patent_app_type] => utility
[patent_app_number] => 17/564902
[patent_app_country] => US
[patent_app_date] => 2021-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 6975
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564902
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/564902 | Stacked FET SRAM design | Dec 28, 2021 | Issued |
Array
(
[id] => 18472691
[patent_doc_number] => 20230206979
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => SENSING COMPONENT WITH A COMMON NODE
[patent_app_type] => utility
[patent_app_number] => 17/646261
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13323
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646261
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/646261 | Sensing component with a common node | Dec 27, 2021 | Issued |
Array
(
[id] => 17536779
[patent_doc_number] => 20220115388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/556268
[patent_app_country] => US
[patent_app_date] => 2021-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15988
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 378
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556268
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/556268 | 2-port SRAM comprising a CFET | Dec 19, 2021 | Issued |
Array
(
[id] => 18950768
[patent_doc_number] => 11894071
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Non-volatile memory with differential temperature compensation for bulk programming
[patent_app_type] => utility
[patent_app_number] => 17/549457
[patent_app_country] => US
[patent_app_date] => 2021-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 38
[patent_no_of_words] => 24860
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549457
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/549457 | Non-volatile memory with differential temperature compensation for bulk programming | Dec 12, 2021 | Issued |
Array
(
[id] => 18890786
[patent_doc_number] => 11869563
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Memory circuits employing source-line and/or bit-line-applied variable programming assist voltages
[patent_app_type] => utility
[patent_app_number] => 17/547298
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 11975
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547298
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/547298 | Memory circuits employing source-line and/or bit-line-applied variable programming assist voltages | Dec 9, 2021 | Issued |
Array
(
[id] => 18097078
[patent_doc_number] => 20220415419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/531458
[patent_app_country] => US
[patent_app_date] => 2021-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531458
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/531458 | Memory device and operating method thereof | Nov 18, 2021 | Issued |
Array
(
[id] => 18287153
[patent_doc_number] => 20230102625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR
[patent_app_type] => utility
[patent_app_number] => 17/529817
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5416
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529817
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529817 | SRAM device including oxide semiconductor | Nov 17, 2021 | Issued |
Array
(
[id] => 18839980
[patent_doc_number] => 11848059
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Techniques for erasing the memory cells of edge word lines
[patent_app_type] => utility
[patent_app_number] => 17/529722
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 24
[patent_no_of_words] => 12936
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529722
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529722 | Techniques for erasing the memory cells of edge word lines | Nov 17, 2021 | Issued |
Array
(
[id] => 18024035
[patent_doc_number] => 20220375534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/517015
[patent_app_country] => US
[patent_app_date] => 2021-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10553
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517015
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/517015 | Memory device configured to apply first and second pass voltages to unselected word lines based on an operating voltage | Nov 1, 2021 | Issued |
Array
(
[id] => 18333800
[patent_doc_number] => 20230125748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => PROACTIVE EDGE WORD LINE LEAK DETECTION FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
[patent_app_type] => utility
[patent_app_number] => 17/511966
[patent_app_country] => US
[patent_app_date] => 2021-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13045
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511966
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/511966 | Proactive edge word line leak detection for memory apparatus with on-pitch semi-circle drain side select gate technology | Oct 26, 2021 | Issued |
Array
(
[id] => 18338445
[patent_doc_number] => 20230130394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => EDGE WORD LINE DATA RETENTION IMPROVEMENT FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
[patent_app_type] => utility
[patent_app_number] => 17/511818
[patent_app_country] => US
[patent_app_date] => 2021-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511818
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/511818 | Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology | Oct 26, 2021 | Issued |
Array
(
[id] => 18338416
[patent_doc_number] => 20230130365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => TRANSFER LATCH TIERS
[patent_app_type] => utility
[patent_app_number] => 17/507606
[patent_app_country] => US
[patent_app_date] => 2021-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15042
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507606
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/507606 | Transfer latch tiers | Oct 20, 2021 | Issued |
Array
(
[id] => 17691871
[patent_doc_number] => 20220199164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => MEMORY DEVICE THAT PERFORMS ERASE OPERATION TO PRESERVE DATA RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 17/503197
[patent_app_country] => US
[patent_app_date] => 2021-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13659
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503197
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/503197 | Memory device that performs erase operation to preserve data reliability | Oct 14, 2021 | Issued |
Array
(
[id] => 18669715
[patent_doc_number] => 11776625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Boost-assisted memory cell selection in a memory array
[patent_app_type] => utility
[patent_app_number] => 17/496667
[patent_app_country] => US
[patent_app_date] => 2021-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 10246
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496667
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/496667 | Boost-assisted memory cell selection in a memory array | Oct 6, 2021 | Issued |
Array
(
[id] => 18431425
[patent_doc_number] => 11676652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Wordline boost driver
[patent_app_type] => utility
[patent_app_number] => 17/450227
[patent_app_country] => US
[patent_app_date] => 2021-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7048
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450227
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450227 | Wordline boost driver | Oct 6, 2021 | Issued |
Array
(
[id] => 17917214
[patent_doc_number] => 20220319610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/492814
[patent_app_country] => US
[patent_app_date] => 2021-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492814
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/492814 | Memory system compensating for performance deterioration of a memory device | Oct 3, 2021 | Issued |