Search

Kretelia Graham

Examiner (ID: 17413, Phone: (571)272-5055 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2615, 2827, 2825, 2817
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 581779 [patent_doc_number] => 07463537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Global bit select circuit interface with dual read and write bit line pairs' [patent_app_type] => utility [patent_app_number] => 11/933625 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1979 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463537.pdf [firstpage_image] =>[orig_patent_app_number] => 11933625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933625
Global bit select circuit interface with dual read and write bit line pairs Oct 31, 2007 Issued
Array ( [id] => 7765523 [patent_doc_number] => 08116161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'System and method for refreshing a DRAM device' [patent_app_type] => utility [patent_app_number] => 11/872675 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 4094 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/116/08116161.pdf [firstpage_image] =>[orig_patent_app_number] => 11872675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872675
System and method for refreshing a DRAM device Oct 14, 2007 Issued
Array ( [id] => 4796431 [patent_doc_number] => 20080008017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'High-performance memory and related method' [patent_app_type] => utility [patent_app_number] => 11/861267 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5782 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20080008017.pdf [firstpage_image] =>[orig_patent_app_number] => 11861267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861267
High-performance memory and related method Sep 24, 2007 Issued
Array ( [id] => 4898055 [patent_doc_number] => 20080117668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'PHASE CHANGE MEMORY DEVICE HAVING A UNIFORM SET AND RESET CURRENT' [patent_app_type] => utility [patent_app_number] => 11/854772 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2982 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117668.pdf [firstpage_image] =>[orig_patent_app_number] => 11854772 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/854772
Phase change memory device having a uniform set and reset current Sep 12, 2007 Issued
Array ( [id] => 4584670 [patent_doc_number] => 07826285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Memory column redundancy scheme' [patent_app_type] => utility [patent_app_number] => 11/853892 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5299 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826285.pdf [firstpage_image] =>[orig_patent_app_number] => 11853892 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853892
Memory column redundancy scheme Sep 11, 2007 Issued
Array ( [id] => 4914304 [patent_doc_number] => 20080094904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'FLASH MEMORY DEVICE OPERATING AT MULTIPLE SPEEDS' [patent_app_type] => utility [patent_app_number] => 11/853958 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3599 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094904.pdf [firstpage_image] =>[orig_patent_app_number] => 11853958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853958
Flash memory device operating at multiple speeds Sep 11, 2007 Issued
Array ( [id] => 26211 [patent_doc_number] => 07796461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Semiconductor device having a plurality of memory chips' [patent_app_type] => utility [patent_app_number] => 11/854248 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6692 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/796/07796461.pdf [firstpage_image] =>[orig_patent_app_number] => 11854248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/854248
Semiconductor device having a plurality of memory chips Sep 11, 2007 Issued
Array ( [id] => 8008375 [patent_doc_number] => 08085596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Reducing noise in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/853578 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6852 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/085/08085596.pdf [firstpage_image] =>[orig_patent_app_number] => 11853578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853578
Reducing noise in semiconductor devices Sep 10, 2007 Issued
Array ( [id] => 4548927 [patent_doc_number] => 07876638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Storing operational information in an array of memory cells' [patent_app_type] => utility [patent_app_number] => 11/853460 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8150 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876638.pdf [firstpage_image] =>[orig_patent_app_number] => 11853460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853460
Storing operational information in an array of memory cells Sep 10, 2007 Issued
Array ( [id] => 4958942 [patent_doc_number] => 20080273366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY' [patent_app_type] => utility [patent_app_number] => 11/851408 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273366.pdf [firstpage_image] =>[orig_patent_app_number] => 11851408 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851408
DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY Sep 6, 2007 Abandoned
Array ( [id] => 279054 [patent_doc_number] => 07558136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability' [patent_app_type] => utility [patent_app_number] => 11/838341 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4909 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558136.pdf [firstpage_image] =>[orig_patent_app_number] => 11838341 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838341
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability Aug 13, 2007 Issued
Array ( [id] => 4521205 [patent_doc_number] => 07933155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Memory device with reduced buffer current during power-down mode' [patent_app_type] => utility [patent_app_number] => 12/161818 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/933/07933155.pdf [firstpage_image] =>[orig_patent_app_number] => 12161818 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/161818
Memory device with reduced buffer current during power-down mode Aug 12, 2007 Issued
Array ( [id] => 5044778 [patent_doc_number] => 20070263450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits' [patent_app_type] => utility [patent_app_number] => 11/781917 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9244 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263450.pdf [firstpage_image] =>[orig_patent_app_number] => 11781917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781917
Non-volatile memory and method with shared processing for an aggregate of read/write circuits Jul 22, 2007 Issued
Array ( [id] => 4801612 [patent_doc_number] => 20080013199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Magnetic Memory Device and Method for Magnetic Reading and Writing' [patent_app_type] => utility [patent_app_number] => 11/772681 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3042 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20080013199.pdf [firstpage_image] =>[orig_patent_app_number] => 11772681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772681
Magnetic Memory Device and Method for Magnetic Reading and Writing Jul 1, 2007 Abandoned
Array ( [id] => 85787 [patent_doc_number] => 07742334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Nonvolatile semiconductor memory device for writing multivalued data' [patent_app_type] => utility [patent_app_number] => 11/819016 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 21983 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742334.pdf [firstpage_image] =>[orig_patent_app_number] => 11819016 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819016
Nonvolatile semiconductor memory device for writing multivalued data Jun 24, 2007 Issued
Array ( [id] => 323688 [patent_doc_number] => 07518929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Nonvolatile semiconductor memory device for writing multivalued data' [patent_app_type] => utility [patent_app_number] => 11/819015 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 21986 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518929.pdf [firstpage_image] =>[orig_patent_app_number] => 11819015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819015
Nonvolatile semiconductor memory device for writing multivalued data Jun 24, 2007 Issued
Array ( [id] => 5209365 [patent_doc_number] => 20070247949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Semiconductor memory device and refresh method for the same' [patent_app_type] => utility [patent_app_number] => 11/812420 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8905 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247949.pdf [firstpage_image] =>[orig_patent_app_number] => 11812420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/812420
Semiconductor memory device and refresh method for the same Jun 18, 2007 Issued
Array ( [id] => 4757983 [patent_doc_number] => 20080310209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Circuit, biasing scheme and fabrication method for diode accesed cross-point resistive memory array' [patent_app_type] => utility [patent_app_number] => 11/812004 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4484 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310209.pdf [firstpage_image] =>[orig_patent_app_number] => 11812004 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/812004
Circuit, biasing scheme and fabrication method for diode accessed cross-point resistive memory array Jun 13, 2007 Issued
Array ( [id] => 5124749 [patent_doc_number] => 20070237020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'WRITE CONTROL CIRCUITRY AND METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS' [patent_app_type] => utility [patent_app_number] => 11/762833 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20070237020.pdf [firstpage_image] =>[orig_patent_app_number] => 11762833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762833
Write control circuitry and method for a memory array configured with multiple memory subarrays Jun 13, 2007 Issued
Array ( [id] => 4931674 [patent_doc_number] => 20080002449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Dynamic random accesss memory and memory for accessing the same' [patent_app_type] => utility [patent_app_number] => 11/811746 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002449.pdf [firstpage_image] =>[orig_patent_app_number] => 11811746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/811746
Dynamic random access memory and method for accessing same Jun 10, 2007 Issued
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