Search

Kretelia Graham

Examiner (ID: 7064)

Most Active Art Unit
2827
Art Unit(s)
2825, 2615, 2817, 2827
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4948220 [patent_doc_number] => 20080304346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Apparatus and method reducing aging in a data storage device' [patent_app_type] => utility [patent_app_number] => 11/810730 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5154 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20080304346.pdf [firstpage_image] =>[orig_patent_app_number] => 11810730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810730
Apparatus and method reducing aging in a data storage device Jun 6, 2007 Abandoned
Array ( [id] => 304640 [patent_doc_number] => 07535787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Methods and apparatuses for refreshing non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/810550 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5787 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535787.pdf [firstpage_image] =>[orig_patent_app_number] => 11810550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810550
Methods and apparatuses for refreshing non-volatile memory Jun 5, 2007 Issued
Array ( [id] => 261031 [patent_doc_number] => 07573762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'One time programmable element system in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/759028 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6268 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573762.pdf [firstpage_image] =>[orig_patent_app_number] => 11759028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/759028
One time programmable element system in an integrated circuit Jun 5, 2007 Issued
Array ( [id] => 16060 [patent_doc_number] => 07808839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing' [patent_app_type] => utility [patent_app_number] => 11/810714 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808839.pdf [firstpage_image] =>[orig_patent_app_number] => 11810714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810714
Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Jun 5, 2007 Issued
Array ( [id] => 4951037 [patent_doc_number] => 20080307163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'METHOD FOR ACCESSING MEMORY' [patent_app_type] => utility [patent_app_number] => 11/758802 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3036 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307163.pdf [firstpage_image] =>[orig_patent_app_number] => 11758802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758802
METHOD FOR ACCESSING MEMORY Jun 5, 2007 Abandoned
Array ( [id] => 7704041 [patent_doc_number] => 08089804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Non-volatile semiconductor memory device using weak cells as reading identifier' [patent_app_type] => utility [patent_app_number] => 11/810554 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6144 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/089/08089804.pdf [firstpage_image] =>[orig_patent_app_number] => 11810554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810554
Non-volatile semiconductor memory device using weak cells as reading identifier Jun 5, 2007 Issued
Array ( [id] => 4506897 [patent_doc_number] => 07920409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-05 [patent_title] => 'SRAM cell with intrinsically high stability and low leakage' [patent_app_type] => utility [patent_app_number] => 11/758568 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6719 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920409.pdf [firstpage_image] =>[orig_patent_app_number] => 11758568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758568
SRAM cell with intrinsically high stability and low leakage Jun 4, 2007 Issued
Array ( [id] => 4712844 [patent_doc_number] => 20080301370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Memory Module' [patent_app_type] => utility [patent_app_number] => 11/757770 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3810 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301370.pdf [firstpage_image] =>[orig_patent_app_number] => 11757770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757770
Memory Module Jun 3, 2007 Abandoned
Array ( [id] => 4590365 [patent_doc_number] => 07852653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Content addressable memory' [patent_app_type] => utility [patent_app_number] => 11/810124 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9010 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852653.pdf [firstpage_image] =>[orig_patent_app_number] => 11810124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810124
Content addressable memory Jun 3, 2007 Issued
Array ( [id] => 4712836 [patent_doc_number] => 20080301362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Content addressable memory address resolver' [patent_app_type] => utility [patent_app_number] => 11/810072 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301362.pdf [firstpage_image] =>[orig_patent_app_number] => 11810072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/810072
Content addressable memory address resolver Jun 3, 2007 Issued
Array ( [id] => 192039 [patent_doc_number] => 07643358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Non volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/756936 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/643/07643358.pdf [firstpage_image] =>[orig_patent_app_number] => 11756936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756936
Non volatile semiconductor memory device May 31, 2007 Issued
Array ( [id] => 5009555 [patent_doc_number] => 20070280033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'METHODS AND DEVICES FOR REGULATING THE TIMING OF CONTROL SIGNALS IN INTEGRATED CIRCUIT MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/756750 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6793 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20070280033.pdf [firstpage_image] =>[orig_patent_app_number] => 11756750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756750
Methods and devices for regulating the timing of control signals in integrated circuit memory devices May 31, 2007 Issued
Array ( [id] => 4577101 [patent_doc_number] => 07848138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Biasing a phase change memory device' [patent_app_type] => utility [patent_app_number] => 11/809702 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/848/07848138.pdf [firstpage_image] =>[orig_patent_app_number] => 11809702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/809702
Biasing a phase change memory device May 31, 2007 Issued
Array ( [id] => 364804 [patent_doc_number] => 07483287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/790529 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19488 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483287.pdf [firstpage_image] =>[orig_patent_app_number] => 11790529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790529
Semiconductor memory Apr 25, 2007 Issued
Array ( [id] => 5003710 [patent_doc_number] => 20070201277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device' [patent_app_type] => utility [patent_app_number] => 11/789624 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4644 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201277.pdf [firstpage_image] =>[orig_patent_app_number] => 11789624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/789624
NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device Apr 24, 2007 Abandoned
Array ( [id] => 8631420 [patent_doc_number] => 08363504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Device and method for state retention power gating' [patent_app_type] => utility [patent_app_number] => 12/595372 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12595372 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/595372
Device and method for state retention power gating Apr 19, 2007 Issued
Array ( [id] => 56352 [patent_doc_number] => 07768845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Memory having circuitry to directly change voltages applied to bit lines and word lines in response to transitions between a read operation, first rewrite operation, and second rewrite operation' [patent_app_type] => utility [patent_app_number] => 11/727466 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10323 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768845.pdf [firstpage_image] =>[orig_patent_app_number] => 11727466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727466
Memory having circuitry to directly change voltages applied to bit lines and word lines in response to transitions between a read operation, first rewrite operation, and second rewrite operation Mar 26, 2007 Issued
Array ( [id] => 4738519 [patent_doc_number] => 20080232171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Phase change memory with program/verify function' [patent_app_type] => utility [patent_app_number] => 11/726852 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4505 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232171.pdf [firstpage_image] =>[orig_patent_app_number] => 11726852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726852
Phase change memory with program/verify function Mar 22, 2007 Issued
Array ( [id] => 5099962 [patent_doc_number] => 20070183223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Memory block erasing in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/726832 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4662 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183223.pdf [firstpage_image] =>[orig_patent_app_number] => 11726832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726832
Memory block erasing in a flash memory device Mar 22, 2007 Issued
Array ( [id] => 4780798 [patent_doc_number] => 20080288797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Method and apparatus for power reduction on a processor bus' [patent_app_type] => utility [patent_app_number] => 11/726910 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3424 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288797.pdf [firstpage_image] =>[orig_patent_app_number] => 11726910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726910
Method and apparatus for power reduction on a processor bus Mar 21, 2007 Issued
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